Nicola Da Dalt
According to our database1,
Nicola Da Dalt
authored at least 26 papers
between 2002 and 2015.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2015
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique.
Int. J. Circuit Theory Appl., 2015
F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
IEEE J. Solid State Circuits, 2013
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
2010
IEEE J. Solid State Circuits, 2010
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.
IEEE J. Solid State Circuits, 2005
A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS.
IEEE J. Solid State Circuits, 2005
2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
IEEE J. Solid State Circuits, 2003
2002
A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology.
IEEE J. Solid State Circuits, 2002