Nicola Bombieri

Hiren D. Patel

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

On the Pose Estimation Software for Measuring Movement Features in the Finger-to-Nose Test.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Digital Health, 2022

Process-driven Collision Prediction in Human-Robot Work Environments.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Emerging Technologies and Factory Automation, 2022

Preserving Data Privacy and Accuracy of Human Pose Estimation Software Based on CNN s for Remote Gait Analysis.

[BibT_eX]

[DOI]

Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022

Real-time Human Pose Estimation at the Edge for Gait Analysis at a Distance.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Distributed Computing in Sensor Systems, 2022

2021

SystemC Implementation of Stochastic Petri Nets for Simulation and Parameterization of Biological Networks.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2021

Task Mapping and Scheduling for OpenVX Applications on Heterogeneous Multi/Many-Core Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

A Container-based Design Methodology for Robotic Applications on Kubernetes Edge-Cloud architectures.

[BibT_eX]

[DOI]

Proceedings of the 24th Forum on specification & Design Languages, 2021

A containerized ROS-compliant verification environment for robotic systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms.

[BibT_eX]

[DOI]

Francesco Lumpp

Hiren D. Patel

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Mangrove: An Inference-Based Dynamic Invariant Mining for GPU Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

CRISPRitz: rapid, high-throughput and variant-aware in silico off-target site identification for CRISPR genome editing.

[BibT_eX]

[DOI]

Bioinform., 2020

On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core Architectures.

[BibT_eX]

[DOI]

Hiren D. Patel

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Late Breaking Results: Enabling Containerized Computing and Orchestration of ROS-based Robotic SW Applications on Cloud-Server-Edge Architectures.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors.

[BibT_eX]

[DOI]

Sara Vinco

Daniele Jahier Pagliari

Enrico Macii

Massimo Poncino

ACM Trans. Design Autom. Electr. Syst., 2019

Parallel Searching on Biological Networks.

[BibT_eX]

[DOI]

Vincenzo Bonnici

Rosalba Giugno

Proceedings of the 27th Euromicro International Conference on Parallel, 2019

Data Flow ORB-SLAM for Real-time Performance on Embedded GPU Boards.

[BibT_eX]

[DOI]

Domenico Daniele Bloisi

Proceedings of the 2019 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2019

Configuring Graph Traversal Applications for GPUs: Analysis of Implementation Strategies and their Correlation with Graph Characteristics.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

RTL Assertion Mining with Automated RTL-to-TLM Abstraction.

[BibT_eX]

[DOI]

Proceedings of the 2019 Forum for Specification and Design Languages, 2019

Efficient Simulation and Parametrization of Stochastic Petri Nets in SystemC: A Case study from Systems Biology.

[BibT_eX]

[DOI]

Proceedings of the 2019 Forum for Specification and Design Languages, 2019

Automatic Parameterization of the Purine Metabolism Pathway through Discrete Event-based Simulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computational Intelligence in Bioinformatics and Computational Biology, 2019

On the Simulation and Automatic Parametrization of Metabolic Networks Through Electronic Design Automation.

[BibT_eX]

[DOI]

Proceedings of the Computational Intelligence Methods for Bioinformatics and Biostatistics, 2019

2018

Pro++: A Profiling Framework for Primitive-Based GPU Programming.

[BibT_eX]

[DOI]

José Manuel López Vilariño

IEEE Trans. Emerg. Top. Comput., 2018

MIRATE: MIps RATional dEsign Science Gateway.

[BibT_eX]

[DOI]

Alessandra Maria Bossi

Sergey Piletsky

Alejandro Giorgetti

J. Integr. Bioinform., 2018

Arena-Idb: a platform to build human non-coding RNA interaction networks.

[BibT_eX]

[DOI]

BMC Bioinform., 2018

Correction to: cuRnet: an R package for graph traversing on GPU.

[BibT_eX]

[DOI]

Alberto Arribas Carmena

BMC Bioinform., 2018

cuRnet: an R package for graph traversing on GPU.

[BibT_eX]

[DOI]

Alberto Arribas Carmena

BMC Bioinform., 2018

Enhancing Performance of Computer Vision Applications on Low-Power Embedded Systems Through Heterogeneous Parallel Programming.

[BibT_eX]

[DOI]

Silvia Manzato

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Rapid Prototyping of Embedded Vision Systems: Embedding Computer Vision Applications into Low-Power Heterogeneous Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

A Framework for the Design and Simulation of Embedded Vision Applications Based on OpenVX and ROS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Hornet: An Efficient Data Structure for Dynamic Sparse Graphs and Matrices on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018

Efficient Load Balancing Techniques for Graph Traversal Applications on GPUs.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2018: Parallel Processing, 2018

An Efficient Implementation of a Subgraph Isomorphism Algorithm for GPUs.

[BibT_eX]

[DOI]

Vincenzo Bonnici

Rosalba Giugno

Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2018

2017

A Dynamic Approach for Workload Partitioning on GPU Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

An Efficient Approach for Accelerating Bucket Elimination on GPUs.

[BibT_eX]

[DOI]

Filippo Bistaffa

IEEE Trans. Cybern., 2017

Integrating Simulink, OpenVX, and ROS for Model-Based Design of Embedded Vision Applications.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Extending OpenVX for model-based design of embedded vision applications.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

A performance, power, and energy efficiency analysis of load balancing techniques for GPUs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

Quickly finding a truss in a haystack.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Fast and Power-Efficient Embedded Software Implementation of Digital Image Stabilization for Low-Cost Autonomous Boats.

[BibT_eX]

[DOI]

Domenico Daniele Bloisi

Jason J. Blum

Proceedings of the Field and Service Robotics, 2017

Power-aware Performance Tuning of GPU Applications Through Microbenchmarking.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

An Efficient Implementation of the Bellman-Ford Algorithm for Kepler GPU Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2016

APPAGATO: an APproximate PArallel and stochastic GrAph querying TOol for biological networks.

[BibT_eX]

[DOI]

Bioinform., 2016

MIPP: A microbenchmark suite for performance, power, and energy consumption characterization of GPU architectures.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

A SystemC-based platform for assertion-based verification and mutation analysis in systems biology.

[BibT_eX]

[DOI]

Proceedings of the 17th Latin-American Test Symposium, 2016

SyQUAL: a platform for qualitative modelling and simulation of biological systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Parametric Multi-step Scheme for GPU-Accelerated Graph Decomposition into Strongly Connected Components.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2016: Parallel Processing Workshops, 2016

CUBE: A CUDA Approach for Bucket Elimination on GPUs.

[BibT_eX]

[DOI]

Filippo Bistaffa

Proceedings of the ECAI 2016 - 22nd European Conference on Artificial Intelligence, 29 August-2 September 2016, The Hague, The Netherlands, 2016

A fine-grained performance model for GPU architectures.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Orienteering-based Path Selection for Mobile Sensors.

[BibT_eX]

[DOI]

Proceedings of the 3rd Italian Workshop on Artificial Intelligence and Robotics, 2016

2015

BFS-4K: An Efficient Implementation of BFS for Kepler GPU Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2015

A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications.

[BibT_eX]

[DOI]

Mirella Negro Marcigaglia

Sara Vinco

ACM Trans. Design Autom. Electr. Syst., 2015

Addressing the Smart Systems design challenge: The SMAC platform.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Reusing RTL Assertion Checkers for Verification of SystemC TLM Models.

[BibT_eX]

[DOI]

J. Electron. Test., 2015

On the Load Balancing Techniques for GPU Applications Based on Prefix-Scan.

[BibT_eX]

[DOI]

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

An Enhanced Profiling Framework for the Analysis and Development of Parallel Primitives for GPUs.

[BibT_eX]

[DOI]

Mirella Negro Marcigaglia

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Exploiting GPU architectures for dynamic invariant mining.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A SystemC Platform for Signal Transduction Modelling and Simulation in Systems Biology.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

RTL property abstraction for TLM assertion-based verification.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Testbench Qualification of SystemC TLM Protocols through Mutation Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

On the reuse of RTL assertions in SystemC TLM verification.

[BibT_eX]

[DOI]

Proceedings of the 15th Latin American Test Workshop, 2014

Optimising memory management for Belief Propagation in Junction Trees using GPGPUs.

[BibT_eX]

[DOI]

Filippo Bistaffa

Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

A cross-level verification methodology for digital IPs augmented with embedded timing monitors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Dynamic Modeling and Simulation of Leukocyte Integrin Activation through an Electronic Design Automation Framework.

[BibT_eX]

[DOI]

Proceedings of the Computational Methods in Systems Biology, 2014

2013

Semi-Automatic Generation of Device Drivers for Rapid Embedded Platform Development.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation.

[BibT_eX]

[DOI]

Emad Samuel Malki Ebeid

Michele Lora

J. Electron. Test., 2013

RTL IP abstraction into optimized embedded software.

[BibT_eX]

[DOI]

Proceedings of the East-West Design & Test Symposium, 2013

SMAC: Smart Systems Co-design.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

On the use of GP-GPUs for accelerating compute-intensive EDA applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

On the automatic generation of GPU-oriented software applications from RTL IPs.

[BibT_eX]

[DOI]

Sara Vinco

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012

On the Reuse of TLM Mutation Analysis at RTL.

[BibT_eX]

[DOI]

Giuseppe Di Guglielmo

J. Electron. Test., 2012

FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2012

Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

On the Reuse of RTL IPs for SysML Model Generation.

[BibT_eX]

[DOI]

Emad Samuel Malki Ebeid

Michele Lora

Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

Energy aware TLM platform simulation via RTL abstraction.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

On the automatic synthesis of parallel SW from RTL models of hardware IPs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

From RTL IP to functional system-level models with extra-functional properties.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

SystemC simulation on GP-GPUs: CUDA vs. OpenCL.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Mutation analysis for SystemC designs at TLM.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

Efficient implementation and abstraction of systemc data types for fast simulation.

[BibT_eX]

[DOI]

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Automatic Interface Generation for Component Reuse in HW-SW Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

System/network design-space exploration based on TLM for networked embedded systems.

[BibT_eX]

[DOI]

Davide Quaglia

ACM Trans. Embed. Comput. Syst., 2010

HIFSuite: Tools for HDL Code Conversion and Manipulation.

[BibT_eX]

[DOI]

Giuseppe Di Guglielmo

Alessandro Venturelli

EURASIP J. Embed. Syst., 2010

Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

HIFSuite: Tools for HDL code conversion and manipulation.

[BibT_eX]

[DOI]

Giuseppe Di Guglielmo

Alessandro Venturelli

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Automatic synthesis of OSCI TLM-2.0 models into RTL bus-based IPs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Abstraction of RTL IPs into embedded software.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

On the Mutation Analysis of SystemC TLM-2.0 Standard.

[BibT_eX]

[DOI]

Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

Correct-by-construction generation of device drivers based on RTL testbenches.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Functional qualification of TLM verification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Automatic customization of device drivers for IP-cores used with assorted CPU organizations.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008

Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

RTL-TLM equivalence checking based on simulation.

[BibT_eX]

[DOI]

Proceedings of the 2008 East-West Design & Test Symposium, 2008

A Mutation Model for the SystemC TLM 2.0 Communication Interfaces.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation.

[BibT_eX]

[DOI]

Nicola Deganello

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Hybrid, Incremental Assertion-Based Verification for TLM Design Flows.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

Towards Equivalence Checking Between TLM and RTL Models.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Incremental ABV for functional validation of TL-to-RTL design refinement.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Hardware Design and Simulation for Verification.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods for Hardware Verification, 2006

A methodology for abstracting RTL designs into TL descriptions.

[BibT_eX]

[DOI]

Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

On the Automatic Transactor Generation for TLM-based Design Flows.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

TLM/network design space exploration for networked embedded systems.

[BibT_eX]

[DOI]

Davide Quaglia

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling.

[BibT_eX]

[DOI]

Andrea Fedeli

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling.

[BibT_eX]

[DOI]

Andrea Fedeli

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Functional Verification of Networked Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004

At-Speed Functional Verification of Programmable Devices.

[BibT_eX]

[DOI]