Nico Jossart
According to our database1,
Nico Jossart
authored at least 8 papers
between 2018 and 2024.
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Bibliography
2024
A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays.
Proceedings of the IEEE International Memory Workshop, 2024
2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application.
Proceedings of the IEEE International Memory Workshop, 2021
2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018