Nick Kanopoulos

Proceedings of the Integrated Circuit and System Design, 2004

2000

Development of reusable serial FIR filters with reprogrammable coefficients designed for serial dataflow architectures.

[BibT_eX]

[DOI]

Kostas Adaos

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999

Testability Concepts and DFT.

[BibT_eX]

[DOI]

Proceedings of the VLSI Handbook., 1999

Efficient implementation of a serial/parallel multiplier for IP based development and rapid prototyping in VLSI digital signal processing.

[BibT_eX]

[DOI]

Kostas Adaos

G. Ph. Alexiou

Nikos Kanopoulos

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

A dual rail circuits synthesis environment for the implementation of multiple output boolean functions.

[BibT_eX]

[DOI]

Theodore Karoubalis

Int. J. Circuit Theory Appl., 1998

An Extensible, Low Cost Rapid Prototyping Environment Based on a Reconfigurable Set of FPGAs.

[BibT_eX]

[DOI]

Kostas Adaos

Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

1996

TESPAD: a testability specifications advisor for a structured test methodology.

[BibT_eX]

[DOI]

W. Weber

Michael G. McNamer

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Automatic synthesis of an 8-bit CPU with 100% on-line error detection capability.

[BibT_eX]

[DOI]

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

A versatile wireless system for real-time telemetry applications.

[BibT_eX]

[DOI]

Theodoros Antonakopoulos

C. Powers

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995

A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1995

Reducing the Time to Market Through Rapid Prototyping - Guest Editors' Introduction.

[BibT_eX]

[DOI]

Apostolos Dollas

Computer, 1995

Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs).

[BibT_eX]

[DOI]

Theodore Karoubalis

Proceedings of the Proceedings EURO-DAC'95, 1995

Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.

[BibT_eX]

[DOI]

Jason P. Hurst

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations.

[BibT_eX]

[DOI]

Mark Royals

IEEE Trans. Very Large Scale Integr. Syst., 1994

Multiple boundary scan-paths for minimizing circuit-board test-application time.

[BibT_eX]

[DOI]

Theodoros Antonakopoulos

Microprocess. Microprogramming, 1994

On the design of a high-performance, expandable, sorting engine.

[BibT_eX]

[DOI]

Dimitrios Stiliadis

Integr., 1994

Design and Implementation of a High-Performance, Modular, Sorting Engine.

[BibT_eX]

[DOI]

Dimitrios Stiliadis

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Efficient board interconnect testing using the split boundary scan register.

[BibT_eX]

[DOI]

Nazar S. Haider

J. Electron. Test., 1993

1992

Design of Self-Checking Circuits Using DCVS Logic: A Case Study.

[BibT_eX]

[DOI]

Dimitris Pantzartzis

Frederick R. Bartram

IEEE Trans. Computers, 1992

A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port.

[BibT_eX]

[DOI]

Mark Royals

Microprocess. Microprogramming, 1992

Design and implementation of a totally self-checking 16 × 16 bit array multiplier.

[BibT_eX]

[DOI]

Joseph H. Carabetta

Integr., 1992

A new serial/parallel two's complement multiplier for vlsi digital signal processing.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1992

The split boundary scan register technique for testing board interconnects.

[BibT_eX]

[DOI]

Nazar S. Haider

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1990

A bus-monitor unit for fault-tolerant system configurations.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1990

On Distributed Fault Simulation.

[BibT_eX]

[DOI]

Mark Royals

Computer, 1990

Creating the IC palette [ASIC design].

[BibT_eX]

[DOI]

Proceedings of the First International Workshop on Rapid System Prototyping, 1990

1989

On the design of a real-time digital median filter.

[BibT_eX]

[DOI]

J. Dodrill

Microprocessing and Microprogramming, 1989

A built-in test module for fault isolation.

[BibT_eX]

[DOI]

Nagesh Vasanthavada

IEEE Des. Test, 1989

The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability.

[BibT_eX]

[DOI]

Computer, 1989

1988

Design of an image edge detection filter using the Sobel operator.

[BibT_eX]

[DOI]

Nagesh Vasanthavada

Robert L. Baker

IEEE J. Solid State Circuits, April, 1988

Design of a bus-monitor for real-time applications.

[BibT_eX]

[DOI]

Peter N. Marinos

Microprocess. Microprogramming, 1988

CAD Tools for Supporting System Design for Testability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

1987

A monolithic scan-line bit producer for real-time image rasterization.

[BibT_eX]

[DOI]

Nagesh Vasanthavada

Microprocess. Microprogramming, 1987

1986

A High-Performance Single-Chip VLSI Signal Processor Architecture.

[BibT_eX]

[DOI]

Peter N. Marinos

Proceedings of the VLSI Algorithms and Architectures, 1986

1985

A single-chip adaptive delta modulator with optimum performance.

[BibT_eX]

[DOI]

Vassilios Makios

Integr., 1985

1984

Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors.

[BibT_eX]

[DOI]

Nikos Kanopoulos

G. Thomas Mitchell

IEEE Des. Test, 1984

1983

Testing of Bit-Serial Signal Processors.

[BibT_eX]