Nicholas Sutardja

According to our database, Nicholas Sutardja authored at least 8 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit.

Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, Elad Alon

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2017

Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology.

Jaeduk Han, Nicholas Sutardja, Yue Lu, Elad Alon

IEEE J. Solid State Circuits, 2017

6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology.

Jaeduk Han, Yue Lu, Nicholas Sutardja, Elad Alon

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.

Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic

IEEE J. Solid State Circuits, 2016

Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology.

Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon

IEEE J. Solid State Circuits, 2016

2015

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic

Proceedings of the Symposium on VLSI Circuits, 2015

A 60Gb/s 173mW receiver frontend in 65nm CMOS technology.

Jaeduk Han, Yue Lu, Nicholas Sutardja, Kwangmo Jung, Elad Alon

Proceedings of the Symposium on VLSI Circuits, 2015

2013

BAG: a designer-oriented integrated framework for the development of AMS circuit generators.

John Crossley, Alberto Puggelli, Hanh-Phuc Le, B. Yang, R. Nancollas, Kwangmo Jung, Lingkai Kong, Nathan Narevsky, Yue Lu, Nicholas Sutardja, E. J. An, Alberto L. Sangiovanni-Vincentelli, Elad Alon

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013