Niccolò Battezzati

According to our database1, Niccolò Battezzati authored at least 12 papers between 2008 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Bibliography

2012
SURF algorithm in FPGA: A novel architecture for high demanding industrial applications.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications.
Springer, ISBN: 978-1-4419-7594-2, 2011

2010
A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A new framework for the automatic insertion of mitigation structures in circuits netlists.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

An integrated flow for the design of hardened circuits on SRAM-based FPGAs.
Proceedings of the 15th European Test Symposium, 2010

On the mitigation of SET broadening effects in integrated circuits.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Soft errors in Flash-based FPGAs: Analysis methodologies and first results.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices.
Proceedings of the 5th Conference on Computing Frontiers, 2008

A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008


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