Nianzheng Cao

Orcid: 0000-0003-2786-9139

According to our database1, Nianzheng Cao authored at least 12 papers between 2006 and 2025.

Collaborative distances:

Timeline

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2020
2022
2024
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC.
IEEE J. Solid State Circuits, January, 2025

2024

2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022

2021


2020
Efficient AI System Design With Cross-Layer Approximate Computing.
Proc. IEEE, 2020


2018


2011
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.
IEEE J. Solid State Circuits, 2011

2010
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2006
A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006


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