Nian-Ze Lee

According to our database, Nian-Ze Lee authored at least 40 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Summary of the Eighth International Workshop on CPAchecker(CPAchecker 2023).

Marie-Christine Jakobs, Nian-Ze Lee

ACM SIGSOFT Softw. Eng. Notes, April, 2024

A Transferability Study of Interpolation-Based Hardware Model Checking for Software Verification.

Dirk Beyer, Po-Chun Chien, Marek Jankola, Nian-Ze Lee

Proc. ACM Softw. Eng., 2024

Software Verification with CPAchecker 3.0: Tutorial and User Guide (Extended Version).

Daniel Baier, Dirk Beyer, Po-Chun Chien, Marie-Christine Jakobs, Marek Jankola, Matthias Kettl, Nian-Ze Lee, Thomas Lemberger, Marian Lingsch Rosenfeld, Henrik Wachowitz, Philipp Wendler

CoRR, 2024

MoXIchecker: An Extensible Model Checker for MoXI.

Salih Ates, Dirk Beyer, Po-Chun Chien, Nian-Ze Lee

CoRR, 2024

Augmenting Interpolation-Based Model Checking with Auxiliary Invariants (Extended Version).

Dirk Beyer, Po-Chun Chien, Nian-Ze Lee

CoRR, 2024

CPV: A Circuit-Based Program Verifier.

Po-Chun Chien, Nian-Ze Lee

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2024

CPAchecker 2.3 with Strategy Selection - (Competition Contribution).

Daniel Baier, Dirk Beyer, Po-Chun Chien, Marek Jankola, Matthias Kettl, Nian-Ze Lee, Thomas Lemberger, Marian Lingsch Rosenfeld, Martin Spiessl, Henrik Wachowitz, Philipp Wendler

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2024

Btor2-Cert: A Certifying Hardware-Verification Framework Using Software Analyzers.

Zsófia Ádám, Dirk Beyer, Po-Chun Chien, Nian-Ze Lee, Nils Sirrenberg

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2024

Augmenting Interpolation-Based Model Checking with Auxiliary Invariants.

Dirk Beyer, Po-Chun Chien, Nian-Ze Lee

Proceedings of the Model Checking Software - 30th International Symposium, 2024

Software Verification with CPAchecker 3.0: Tutorial and User Guide.

Daniel Baier, Dirk Beyer, Po-Chun Chien, Marie-Christine Jakobs, Marek Jankola, Matthias Kettl, Nian-Ze Lee, Thomas Lemberger, Marian Lingsch Rosenfeld, Henrik Wachowitz, Philipp Wendler

Proceedings of the Formal Methods - 26th International Symposium, 2024

2023

Reproduction Package for TACAS 2024 Submission 'Btor2-Cert: A Certifying Hardware-Verification Framework Using Software Analyzers'.

Zsófia Ádám, Dirk Beyer, Po-Chun Chien, Nian-Ze Lee, Nils Sirrenberg

Dataset, October, 2023

Reproduction Package for JAR Article 'Interpolation and SAT-Based Model Checking Revisited'.

Dirk Beyer, Nian-Ze Lee, Philipp Wendler

Dataset, September, 2023

Reproduction package for VMCAI 2024 submission 'Augmenting Interpolation-Based Model Checking with Auxiliary Invariants'.

Dirk Beyer, Po-Chun Chien, Nian-Ze Lee

Dataset, September, 2023

SoSy-Lab Virtual Machine (Ubuntu 22.04 LTS).

Dirk Beyer, Po-Chun Chien, Nian-Ze Lee

Dataset, August, 2023

Reproduction Package for ASE 2023 Article 'CPA-DF: A Tool for Configurable Interval Analysis to Boost Program Verification'.

Dirk Beyer, Po-Chun Chien, Nian-Ze Lee

Dataset, August, 2023

Reproduction Package for ASE 2023 Tool-Demo Submission 'CPA-DF: A Tool for Configurable Interval Analysis to Boost Program Verification'.

Dirk Beyer, Po-Chun Chien, Nian-Ze Lee

Dataset, May, 2023

Reproduction Package for TACAS 2023 Article 'Bridging Hardware and Software Analysis with Btor2C: A Word-Level-Circuit-to-C Converter'.

Dirk Beyer, Nian-Ze Lee, Po-Chun Chien

Dataset, February, 2023

Bridging Hardware and Software Analysis with Btor2C: A Word-Level-Circuit-to-C Translator.

Dirk Beyer, Po-Chun Chien, Nian-Ze Lee

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2023

CPA-DF: A Tool for Configurable Interval Analysis to Boost Program Verification.

Dirk Beyer, Po-Chun Chien, Nian-Ze Lee

Proceedings of the 38th IEEE/ACM International Conference on Automated Software Engineering, 2023

2022

Reproduction Package for TACAS 2023 Submission 'Bridging Hardware and Software Analysis with Btor2C: A Word-Level-Circuit-to-C Converter'.

Dirk Beyer, Nian-Ze Lee, Po-Chun Chien

Dataset, November, 2022

Reproduction Package for JAR Submission 'Interpolation and SAT-Based Model Checking Revisited'.

Dirk Beyer, Nian-Ze Lee, Philipp Wendler

Dataset, August, 2022

Reproduction Package for CAV 2022 Submission 'Interpolation and SAT-Based Model Checking Revisited'.

Dirk Beyer, Nian-Ze Lee, Philipp Wendler

Dataset, January, 2022

Interpolation and SAT-Based Model Checking Revisited: Adoption to Software Verification.

Dirk Beyer, Nian-Ze Lee, Philipp Wendler

CoRR, 2022

2021

Reproduction Package for ICSE 2022 Submission 'Interpolation and SAT-Based Model Checking Revisited'.

Dirk Beyer, Nian-Ze Lee, Philipp Wendler

Dataset, September, 2021

Constraint Solving for Synthesis and Verification of Threshold Logic Circuits.

Nian-Ze Lee, Jie-Hong R. Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty.

Nian-Ze Lee, Jie-Hong R. Jiang

Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020

Reproduction Package for TACAS 2021 Submission 'Interpolation and SAT-Based Model Checking Revisited'.

Dirk Beyer, Nian-Ze Lee, Philipp Wendler

Dataset, October, 2020

Engineering Change Order for Combinational and Sequential Design Rectification.

Jie-Hong R. Jiang, Victor N. Kravets, Nian-Ze Lee

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Towards a Framework for the Analysis of Multi-Product Lines in the Automotive Domain.

Shaukat Ali, Paolo Arcaini, Ichiro Hasuo, Fuyuki Ishikawa, Nian-Ze Lee

Proceedings of the 13th International Workshop on Variability Modelling of Software-Intensive Systems, 2019

Scenario Sampling for Cyber Physical Systems using Combinatorial Testing.

Akihisa Yamada, Clovis Eberhart, Fuyuki Ishikawa, Nian-Ze Lee

Proceedings of the 2019 IEEE International Conference on Software Testing, 2019

Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks.

Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang

Proceedings of the International Conference on Computer-Aided Design, 2019

Stability analysis for safety of automotive multi-product lines: a search-based approach.

Nian-Ze Lee, Paolo Arcaini, Shaukat Ali, Fuyuki Ishikawa

Proceedings of the Genetic and Evolutionary Computation Conference, 2019

Comprehensive Search for ECO Rectification Using Symbolic Sampling.

Victor N. Kravets, Nian-Ze Lee, Jie-Hong R. Jiang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Towards Formal Evaluation and Verification of Probabilistic Design.

Nian-Ze Lee, Jie-Hong R. Jiang

IEEE Trans. Computers, 2018

Solving Exist-Random Quantified Stochastic Boolean Satisfiability via Clause Selection.

Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang

Proceedings of the Twenty-Seventh International Joint Conference on Artificial Intelligence, 2018

Canonicalization of threshold logic representation and its applications.

Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang

Proceedings of the International Conference on Computer-Aided Design, 2018

Efficient computation of ECO patch functions.

Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Solving Stochastic Boolean Satisfiability under Random-Exist Quantification.

Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang

Proceedings of the Twenty-Sixth International Joint Conference on Artificial Intelligence, 2017

Sequential engineering change order under retiming and resynthesis.

Nian-Ze Lee, Victor N. Kravets, Jie-Hong R. Jiang

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits.

Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang

Proceedings of the 35th International Conference on Computer-Aided Design, 2016