Ni Xu
Orcid: 0000-0002-2507-1708
According to our database1,
Ni Xu
authored at least 23 papers
between 2010 and 2024.
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Bibliography
2024
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2024, 2024
2023
Utilitarian and/or hedonic shopping - consumer motivation to purchase in smart stores.
Ind. Manag. Data Syst., 2023
Factors influencing customers' shopping and word-of-mouth intentions in smart stores.
Int. J. Mob. Commun., 2023
2022
Int. J. Soc. Robotics, 2022
Proceedings of the Advances and Trends in Artificial Intelligence. Theory and Practices in Artificial Intelligence, 2022
Proceedings of the Human Interface and the Management of Information: Applications in Complex Technological Environments, 2022
Proceedings of the Human-Computer Interaction. Technological Innovation, 2022
2021
Proceedings of the Advances and Trends in Artificial Intelligence. From Theory to Practice, 2021
2019
Proceedings of the Mining Intelligence and Knowledge Exploration, 2019
Proceedings of the Data Mining and Big Data - 4th International Conference, 2019
2016
An overview of digital-intensive ΔΣ phase-locked loops utilizing 1-bit conversion and modulation.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
2015
A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation.
IEEE J. Solid State Circuits, 2014
A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
J. Electr. Comput. Eng., 2011
2010
Proceedings of the International Conference on Information and Communication Technology Convergence, 2010
Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2-6GHz software-defined radio frequency synthesis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010