Nesara Eranna Bethur

According to our database, Nesara Eranna Bethur authored at least 4 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs.

Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024

Back-side Design Methodology for Power Delivery Network and Clock Routing.

Pruek Vanna-Iampikul, Hang Yang, Jungyoun Kwak, Joyce X. Hu, Amaan Rahman, Nesara Eranna Bethur, Callie Hao, Shimeng Yu, Sung Kyu Lim

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

GNN-assisted Back-side Clock Routing Methodology for Advance Technologies.

Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2022

3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs.

Lingjun Zhu, Nesara Eranna Bethur, Yi-Chen Lu, Youngsang Cho, Yunhyeok Im, Sung Kyu Lim

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022