Nereo Markulic
Orcid: 0000-0001-6691-4647
According to our database1,
Nereo Markulic
authored at least 29 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE J. Solid State Circuits, June, 2024
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm.
IEEE J. Solid State Circuits, 2021
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion.
IEEE J. Solid State Circuits, 2021
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4<sup>th</sup> Nyquist Zone in 1GS/s ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth.
IEEE J. Solid State Circuits, 2020
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth.
IEEE J. Solid State Circuits, 2019
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation.
IEEE J. Solid State Circuits, 2016
Proceedings of the 39th International Convention on Information and Communication Technology, 2016
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter.
IEEE J. Solid State Circuits, 2015
2014
Proceedings of the ESSCIRC 2014, 2014