Neeta Pandey

ACM Trans. Design Autom. Electr. Syst., 2024

A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications.

[BibT_eX]

[DOI]

Lokesh Soni

Integr., 2024

2023

A Novel Chaotic System with Exponential Nonlinearity and its Adaptive Self-Synchronization: From Numerical Simulations to Circuit Implementation.

[BibT_eX]

[DOI]

Kriti Suneja

J. Circuits Syst. Comput., November, 2023

Modeling of Dual- Metal Junctionless Accumulation-Mode cylindrical surrounding gate (DM-JAM-CSG) MOSFET for cryogenic temperature applications.

[BibT_eX]

[DOI]

Sumedha Gupta

R. S. Gupta

Microelectron. J., September, 2023

Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving Energy Efficiency.

[BibT_eX]

[DOI]

Neetika Yadav

J. Circuits Syst. Comput., August, 2023

Memristor-Based Architectures for PFSCL Circuit Realizations.

[BibT_eX]

[DOI]

Shikha

Circuits Syst. Signal Process., August, 2023

LDML: A Proposal to Reduce Leakage Power in DML Circuits.

[BibT_eX]

[DOI]

Neetika Yadav

Wirel. Pers. Commun., March, 2023

PLC and SCADA based Real Time Monitoring and Train Control System for the Metro Railways Infrastructure.

[BibT_eX]

[DOI]

Ishu Tomar

Indu Sreedevi

Wirel. Pers. Commun., March, 2023

Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell.

[BibT_eX]

[DOI]

Damyanti Singh

Microelectron. J., 2023

CCTA based four different pairs of mutually coupled circuit using single topology.

[BibT_eX]

[DOI]

Navnit Kumar

Manjeet Kumar

Integr., 2023

Electronically tunable positive and negative fractional order inductor circuit using single topology.

[BibT_eX]

[DOI]

Navnit Kumar

Manjeet Kumar

Integr., 2023

Refining RNMC compensation for Three Stage Amplifier using DTMOS Transistor and FFVF.

[BibT_eX]

[DOI]

Om Krishna Gupta

Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2022

On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates.

[BibT_eX]

[DOI]

Ranjana Sivaram

Microprocess. Microsystems, April, 2022

A novel read decoupled 8T1M nvSRAM cell for near threshold operation.

[BibT_eX]

[DOI]

Damyanti Singh

Microelectron. J., 2022

Novel Pehlivan-Uyarŏglu Chaotic System Variants and their CFOA Based Realization.

[BibT_eX]

[DOI]

Kriti Suneja

J. Circuits Syst. Comput., 2022

A novel design of a 1 GHz phase locked loop with improved lock time for fast frequency acquisition.

[BibT_eX]

[DOI]

Monika Bhardwaj

Sujata Pandey

Int. J. Comput. Aided Eng. Technol., 2022

OTA Based Fractional-Order Oscillator With Controlled Phase Difference.

[BibT_eX]

[DOI]

Garima Varshney

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm.

[BibT_eX]

[DOI]

Monica Gupta

Microprocess. Microsystems, September, 2021

Unified floating immittance emulator based on CCTA.

[BibT_eX]

[DOI]

Navnit Kumar

Manjeet Kumar

Microelectron. J., 2021

Clock Aligned Input Adiabatic Logic.

[BibT_eX]

[DOI]

Aditya S. Kumar

Sagar Jain

Microelectron. J., 2021

A novel design for voltage inverting metamutator and its applications.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Leakage reduction in dual mode logic through gated leakage transistors.

[BibT_eX]

[DOI]

Neetika Yadav

Microprocess. Microsystems, 2021

Generalization of shadow filters in fractional domain.

[BibT_eX]

[DOI]

Garima Varshney

Int. J. Circuit Theory Appl., 2021

A novel PVT-variation-tolerant Schmitt-trigger-based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub-threshold region.

[BibT_eX]

[DOI]

Monica Gupta

Int. J. Circuit Theory Appl., 2021

A data-independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub-threshold region.

[BibT_eX]

[DOI]

Monica Gupta

Int. J. Circuit Theory Appl., 2021

2020

A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability.

[BibT_eX]

[DOI]

Microelectron. J., 2020

A new realization scheme for dynamic PFSCL style.

[BibT_eX]

[DOI]

Ranjana Sivaram

Integr., 2020

Model and Design of Improved Current Mode Logic Gates - Differential and Single-ended

[BibT_eX]

[DOI]

Springer, ISBN: 978-981-15-0981-0, 2020

2019

Operational Transresistance Amplifier Based Wienbridge Oscillator and Its Harmonic Analysis.

[BibT_eX]

[DOI]

Gurumurthy Komanapalli

Wirel. Pers. Commun., 2019

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Realization of Resistorless and Electronically Tunable Inverse Filters Using VDTA.

[BibT_eX]

[DOI]

Praveen Kumar

J. Circuits Syst. Comput., 2019

New sinusoidal oscillator configurations using operational transresistance amplifier.

[BibT_eX]

[DOI]

Gurumurthy Komanapalli

Int. J. Circuit Theory Appl., 2019

Programmable CCCII: reliability analysis and design methodology.

[BibT_eX]

[DOI]

Manoj Kumar Tiwari

Saiyid Mohammad Irshad Rizvi

IET Circuits Devices Syst., 2019

Novel Control Unit Design for a High-Speed SHA-3 Architecture.

[BibT_eX]

[DOI]

Pranav Gangwar

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Hardware/Software Co-Design of a High-Speed Othello Solver.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018

Pentavariate V<sub>min</sub> Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read.

[BibT_eX]

[DOI]

Shourya Gupta

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Novel High Speed Vedic Multiplier Proposal Incorporating Adder Based on Quaternary Signed Digit Number System.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

OTRA Based Log and Antilog Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

MCML Dynamic Register Design.

[BibT_eX]

[DOI]

Bharat Choudhary

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Design of an SCL logic based Current Comparator.

[BibT_eX]

[DOI]

Sri Ranjani Prasanthi

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist.

[BibT_eX]

[DOI]

Shourya Gupta

IEEE Trans. Very Large Scale Integr. Syst., 2017

Modified Tang and Pun's Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2017

On Improving the Performance of Dynamic DCVSL Circuits.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2017

New Sleep-Based PFSCL Tri-State Inverter/Buffer Topologies.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2017

Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies.

[BibT_eX]

[DOI]

Proceedings of the Computational Science and Its Applications - ICCSA 2017, 2017

2016

New Proposal for MCML Based Three-Input Logic Implementation.

[BibT_eX]

[DOI]

Bharat Choudhary

VLSI Design, 2016

MOS current mode logic exclusive-OR gate using multi-threshold triple-tail cells.

[BibT_eX]

[DOI]

Microelectron. J., 2016

Generalised operational floating current conveyor based instrumentation amplifier.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2016

Universal biquadratic filter using Operational Floating Current Conveyor (OFCC).

[BibT_eX]

[DOI]

Divyesh Sachan

Proceedings of the 28th International Conference on Microelectronics, 2016

A Novel Bulk Drain Connected 6T SRAM Cell.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computing and Data Sciences, 2016

A Novel Ultra Low Power Current Comparator.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computing and Data Sciences, 2016

2015

Approach for third order quadrature oscillator realisation.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2015

2014

An efficient triple-tail cell based PFSCL D latch.

[BibT_eX]

[DOI]

Microelectron. J., 2014

Novel grounded inductance simulator using single OTRA.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2014

2013

Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells.

[BibT_eX]

[DOI]

Microelectron. J., 2013

Mixed Mode Universal filter.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2013

2012

An expandable current-mode ADC with power optimization technique.

[BibT_eX]

[DOI]

Asok Bhattacharyya

Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012

2011

New Topologies of Lossless Grounded Inductor Using OTRA.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2011

Operational Transresistance Amplifier-Based Multiphase Sinusoidal Oscillators.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2011

Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2011

Single CDTA-Based Current Mode All-Pass Filter and Its Applications.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2011

MO-CCCCTA-Based Floating Positive and Negative Inductors and Their Applications.

[BibT_eX]

[DOI]

Rishik Bazaz

Rahul Manocha

J. Electr. Comput. Eng., 2011

New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2011

2010

SIMO Transadmittance Mode Active-C Universal Filter.

[BibT_eX]

[DOI]

Circuits Syst., 2010

2006

A new mixed mode biquad using reduced number of active and passive elements.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2006

2005

A novel current controlled current mode universal filter: SITO approach.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2005

An insensitive current mode universal biquad: multi-input multi-output.

[BibT_eX]

[DOI]