Neeraj Kumar Shukla

Orcid: 0000-0002-7093-3805

According to our database1, Neeraj Kumar Shukla authored at least 15 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
A unified test data volume compression scheme for circular scan architecture using hosted cuckoo optimization.
J. Supercomput., March, 2024

Speech enhancement system using deep neural network optimized with Battle Royale Optimization.
Biomed. Signal Process. Control., 2024

2023
Metaheuristic Optimization Based Node Localization and Multihop Routing Scheme with Mobile Sink for Wireless Sensor Networks.
Wirel. Pers. Commun., April, 2023

An Intelligent Approach to Determine Component Volume Percentages in a Symmetrical Homogeneous Three-Phase Fluid in Scaled Pipe Conditions.
Symmetry, 2023

Acoustic Wave Reflection in Water Affects Underwater Wireless Sensor Networks.
Sensors, 2023

Quasi-oppositional artificial algae optimization with adaptive neuro fuzzy inference based maximum power point tracking for PV systems.
J. Intell. Fuzzy Syst., 2023

An Efficient MPPT Tracking in Solar PV System with Smart Grid Enhancement Using CMCMAC Protocol.
Comput. Syst. Sci. Eng., 2023

2022
An Enhanced Trust-Based Kalman Filter Route Optimization Technique for Wireless Sensor Networks.
Wirel. Pers. Commun., 2022

High speed integrated RF-VLC data communication system: Performance constraints and capacity considerations.
Phys. Commun., 2022

2021
A field programmable gate array-based biomedical noise reduction framework using advanced trilateral filter.
Trans. Inst. Meas. Control, 2021

2020
A Congestion Controlled and Load Balanced Selection Strategy for Networks on Chip.
Int. J. Distributed Syst. Technol., 2020

Performance Analysis of 8T FinFET SRAM Bit-Cell for Low-power Applications.
Proceedings of the 5th International Conference on Computing, Communication and Security, 2020

2011
Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology.
Circuits Syst., 2011

2010
Analysis and Simulation of a Low Leakage Conventional SRAM Memory Cell at Deep Sub-micron Level.
Proceedings of the Information Processing and Management, 2010

2009
Synthesis and Modeling of Spiral Inductor at 90nm Technology.
Proceedings of the ARTCom 2009, 2009


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