Neelam Surana
Orcid: 0000-0002-7841-8541
According to our database1,
Neelam Surana
authored at least 11 papers
between 2014 and 2023.
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Bibliography
2023
ACM Trans. Archit. Code Optim., June, 2023
2022
A 10T, 0.22fJ/Bit/Search Mixed-V<sub>T</sub> Pseudo Precharge-Free Content Addressable Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
2021
CoRR, 2021
2020
A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder.
IET Comput. Digit. Tech., 2019
Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia Applications.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
2014
In<sub>0</sub> <sub>25</sub>Ga<sub>0</sub> <sub>75</sub>As Channel Double Gate Junctionless Transistor.
J. Low Power Electron., 2014