Necati Uysal

Orcid: 0000-0002-9543-3823

According to our database1, Necati Uysal authored at least 14 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Synthesis of Clock Networks with a Mode-Reconfigurable Topology.
ACM Trans. Design Autom. Electr. Syst., 2022

XMAP: Programming Memristor Crossbars for Analog Matrix-Vector Multiplication: Toward High Precision Using Representable Matrices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Computational Restructuring: Rethinking Image Compression Using Resistive Crossbar Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An OCV-Aware Clock Tree Synthesis Methodology.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

DP-MAP: Towards Resistive Dot-Product Engines with Improved Precision.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Computational Restructuring: Rethinking Image Processing using Memristor Crossbar Arrays.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
STAT: Mean and Variance Characterization for Robust Inference of DNNs on Memristor-based Platforms.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Handling stuck-at-faults in memristor crossbar arrays using matrix transformations.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
OCV guided clock tree topology reconstruction.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018


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