Nazareno Bruschi
According to our database1,
Nazareno Bruschi
authored at least 9 papers
between 2020 and 2024.
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Bibliography
2024
Parallel computing architectures and techniques for heterogeneous acceleration of AI algorithms.
PhD thesis, 2024
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Computers, 2021
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
2020
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020