Navonil Chatterjee

According to our database, Navonil Chatterjee authored at least 26 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Mitigating Transceiver and Token Controller Permanent Faults in Wireless Network-on-Chip.

Navonil Chatterjee, Marcelo Ruaro, Kevin J. M. Martin, Jean-Philippe Diguet

Proceedings of the 30th Euromicro International Conference on Parallel, 2022

2021

Attacks Toward Wireless Network-on-Chip and Countermeasures.

Arnab Kumar Biswas, Navonil Chatterjee, Hemanta Kumar Mondal, Guy Gogniat, Jean-Philippe Diguet

IEEE Trans. Emerg. Top. Comput., 2021

Adaptive Task Allocation and Scheduling on NoC-based Multicore Platforms with Multitasking Processors.

Suraj Paul, Navonil Chatterjee, Prasun Ghosal, Jean-Philippe Diguet

ACM Trans. Embed. Comput. Syst., 2021

VCS: A method of in-order packet delivery for adaptive NoC routing.

Tuhin Subhra Das, Prasun Ghosal, Navonil Chatterjee

Nano Commun. Networks, 2021

Dynamic task allocation and scheduling with contention-awareness for Network-on-Chip based multicore systems.

Suraj Paul, Navonil Chatterjee, Prasun Ghosal

J. Syst. Archit., 2021

A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing.

Suraj Paul, Navonil Chatterjee, Prasun Ghosal, Jean-Philippe Diguet

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Application of Logical Sub-networking in Congestion-aware Deadlock-free SDmesh Routing.

Tuhin Subhra Das, Prasun Ghosal, Navonil Chatterjee, Arnab Nath, Akash Banerjee, Subhojyoti Khastagir

ACM Trans. Embed. Comput. Syst., 2020

Thermal-aware detour routing in 3D NoCs.

Priyajit Mukherjee, Navonil Chatterjee, Santanu Chattopadhyay

J. Parallel Distributed Comput., 2020

Regulating Degree of Adaptiveness for Performance-Centric NoC Routing.

Tuhin Subhra Das, Navonil Chatterjee, Prasun Ghosal

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Broadcast Mechanism Based on Hybrid Wireless/Wired NoC for Efficient Barrier Synchronization in Parallel Computing.

Hemanta Kumar Mondal, Navonil Chatterjee, Rodrigo Cataldo, Jean-Philippe Diguet

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Dynamic Task Mapping and Scheduling with Temperature-Awareness on Network-on-Chip based Multicore Systems.

Suraj Paul, Navonil Chatterjee, Prasun Ghosal

J. Syst. Archit., 2019

A permanent fault tolerant dynamic task allocation approach for Network-on-Chip based multicore systems.

Suraj Paul, Navonil Chatterjee, Prasun Ghosal

J. Syst. Archit., 2019

Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip.

N. Prasad, Navonil Chatterjee, Santanu Chattopadhyay, Indrajit Chakrabarti

CoRR, 2019

CDMA-based multiple multicast communications on WiNOC for efficient parallel computing.

Navonil Chatterjee, Hemanta Kumar Mondal, Rodrigo Cataldo, Jean-Philippe Diguet

Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Virtual circuit switch based orderly delivery of packets in adaptive NoC routing.

Tuhin Subhra Das, Prasun Ghosal, Navonil Chatterjee

Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

2018

Task mapping and scheduling for network-on-chip based multi-core platform with transient faults.

Navonil Chatterjee, Suraj Paul, Santanu Chattopadhyay

J. Syst. Archit., 2018

Reliability-aware application mapping onto mesh based Network-on-Chip.

Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay

Integr., 2018

A Dynamic Resource Allocation Strategy for NoC Based Multicore Systems with Permanent Faults.

Suraj Paul, Navonil Chatterjee, Prasun Ghosal

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform.

Navonil Chatterjee, Suraj Paul, Santanu Chattopadhyay

ACM Trans. Embed. Comput. Syst., 2017

Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform.

Navonil Chatterjee, Suraj Paul, Priyajit Mukherjee, Santanu Chattopadhyay

J. Syst. Archit., 2017

2016

A strategy for fault tolerant reconfigurable Network-on-Chip design.

Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A reliability aware application mapping onto mesh based Network-on-Chip.

Navonil Chatterjee, Sheshivardhan Reddy, Shilpa Reddy, Santanu Chattopadhyay

Proceedings of the 2016 3rd International Conference on Recent Advances in Information Technology (RAIT), 2016

2015

Fault tolerant mesh based Network-on-Chip architecture.

Navonil Chatterjee, Santanu Chattopadhyay

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

A spare link based reliable Network-on-Chip design.

Navonil Chatterjee, N. Prasad, Santanu Chattopadhyay

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

A spare router based reliable Network-on-Chip design.

Navonil Chatterjee, Santanu Chattopadhyay, Kanchan Manna

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012

VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark.

Sudip Ghosh, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee, Hafizur Rahaman, Santi P. Maity

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012