Navjeet Bagga

According to our database, Navjeet Bagga authored at least 14 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Demonstration of a Vertically Stacked Junctionless Forksheet as Dielectric Modulated Biosensor.

Navneet Gandhi, Rajeewa Kumar Jaisawal, P. N. Kondekar, Ankit Dixit, Naveen Kumar, Vihar P. Georgiev, Navjeet Bagga

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

Self-Heating and Process-Induced Threshold Voltage Aware Reliability and Aging Analysis of Forksheet FET.

Sunil Rathore, Navjeet Bagga, S. Dasgupta

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Small Signal Analysis of Nanosheet Transistor for sub-THz Frequency Considering Intersheet Capacitances and Modified Admittance Parameters.

Jyoti Patel, Navjeet Bagga, Vivek Kumar, S. Dasgupta

Proceedings of the Device Research Conference, 2024

2023

Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET.

Sunil Rathore, Rajeewa Kumar Jaisawal, Pravin Neminath Kondekar, Navjeet Bagga

Microelectron. J., September, 2023

Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET.

Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Navneet Gandhi, Shashank Banchhor, Young Suh Song, Navjeet Bagga

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Gate Oxide Induced Reliability Assessment of Junctionless FinFET-Based Hydrogen Gas Sensor.

Navneet Gandhi, Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Ankit Dixit, Naveen Kumar, Vihar P. Georgiev, Navjeet Bagga

Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023

2022

Investigation of geometrical impact on a P⁺ buried negative capacitance SOI FET.

Toushik Santra, Ankit Dixit, Rajeewa Kumar Jaisawal, Sunil Rathore, Saheli Sarkhel, Navjeet Bagga

Microelectron. J., 2022

Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor.

Sunil Rathore, Rajeewa Kumar Jaisawal, Navneet Gandhi, P. N. Kondekar, Navjeet Bagga

Microelectron. J., 2022

Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α).

Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Navjeet Bagga

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective.

Aniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI.

Nitanshu Chauhan, Chirag Garg, Kai Ni, Amit Kumar Behera, Sarita Yadav, Shashank Banchhor, Navjeet Bagga, Avirup Dasgupta, Arnab Datta, Sudeb Dasgupta, Anand Bulusu

Proceedings of the IEEE International Reliability Physics Symposium, 2022

Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage.

Navjeet Bagga, Kai Ni, Nitanshu Chauhan, Om Prakash, X. Sharon Hu, Hussam Amrouch

Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021

Traps Based Reliability Barrier on Performance and Revealing Early Ageing in Negative Capacitance FET.

Aniket Gupta, Govind Bajpai, Priyanshi Singhal, Navjeet Bagga, Om Prakash, Shashank Banchhor, Hussam Amrouch, Nitanshu Chauhan

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020

Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification.

Nitanshu Chauhan, Govind Bajpai, Shashank Banchhor, Navjeet Bagga

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020