Navid Sarhangnejad

Orcid: 0000-0002-4409-6791

According to our database1, Navid Sarhangnejad authored at least 8 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging.
IEEE J. Solid State Circuits, November, 2023

2022
A 39, 000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2019
Dual-Tap Computational Photography Image Sensor With Per-Pixel Pipelined Digital Memory for Intra-Frame Coded Multi-Exposure.
IEEE J. Solid State Circuits, 2019

Dual-Tap Pipelined-Code-Memory Coded-Exposure-Pixel CMOS Image Sensor for Multi-Exposure Single-Frame Computational Imaging.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Superresolution Line Scan Image Sensor for Multimodal Microscopy.
IEEE Trans. Biomed. Circuits Syst., 2018

Coded Two-Bucket Cameras for Computer Vision.
Proceedings of the Computer Vision - ECCV 2018, 2018

2016
6.3 105×65mm2 391Mpixel CMOS image sensor with >78dB dynamic range for airborne mapping applications.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2011
A continuous-time ΣΔ modulator with a Gm-C input stage, 120-dB CMRR and -87 dB THD.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011


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