Naveena Nagi

According to our database, Naveena Nagi authored at least 17 papers between 1992 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

1999

Test Metrics for Analog Parametric Faults.

Stephen K. Sunter, Naveena Nagi

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1998

Signature analysis for analog and mixed-signal circuit test response compaction.

Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits.

Heebyung Yoon, Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling.

Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial.

Abhijit Chatterjee, Naveena Nagi

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST.

Stephen K. Sunter, Naveena Nagi

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996

A unified approach for fault simulation of linear mixed-signal circuits.

Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham

J. Electron. Test., 1996

DC Built-In Self-Test for Linear Analog Circuits.

Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi

IEEE Des. Test Comput., 1996

Low-cost DC built-in self-test of linear analog circuits using checksums.

Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

Efficient multisine testing of analog circuits.

Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994

A Signature Analyzer for Analog and Mixed-signal Circuits.

Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993

Fault simulation of linear analog circuits.

Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham

J. Electron. Test., 1993

MIXER: Mixed-Signal Fault Simulator.

Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Fault-based automatic test generator for linear analog circuits.

Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

DRAFTS: Discretized Analog Circuit Fault Simulator.

Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Delay fault testing of iterative arithmetic arrays.

Rabindra K. Roy, Naveena Nagi, Abhijit Chatterjee, Manuel A. d'Abreu

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Hierarchical fault modeling for analog and mixed-signal circuits.

Naveena Nagi, Jacob A. Abraham

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992