Naveen Kadayinti

Orcid: 0000-0003-0859-9380

According to our database1, Naveen Kadayinti authored at least 10 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2023
Mismatch Tolerant Negative Conductance Load Tuning for High Gain OTAs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
A True Time Delay Element using Cascaded Variable Bandwidth All Pass Filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2018
Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects.
Microelectron. J., 2018

2017
Sense amplifier comparator with offset correction for decision feedback equalization based receivers.
Microelectron. J., 2017

Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital Converter.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A Clock Retiming Circuit for Repeaterless Low Swing On-Chip Interconnects.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Settling time of mesochronous clock re-timing circuits in the presence of timing jitter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Settling Time of Mesochronous Clock Retiming Circuits for Low Swing Interconnects.
CoRR, 2016

2015
Testable Design of Repeaterless Low Swing On-Chip Interconnect.
CoRR, 2015

A Clock Synchronizer for Repeaterless Low Swing On-Chip Links.
CoRR, 2015


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