Natsuo Ajika

According to our database, Natsuo Ajika authored at least 4 papers between 1989 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A 58-nm 2-Gb MLC "B4-Flash" Memory with Flexible Multisector Architecture.

Taku Ogura, Yasushi Kasa, Kazuhide Kurosaki, Mitsuhiro Tomoeda, Hisakazu Otoi, Satoshi Shimizu, Masafumi Katsumata, Natsuo Ajika, Kazuo Kobayashi

IEEE J. Solid State Circuits, 2017

1999

A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications.

Atsushi Nozoe, Hiroaki Kotani, Tetsuya Tsujikawa, Keiichi Yoshida, Kazunori Furusawa, Masataka Kato, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Kurata, Naoki Miyamoto, Shoji Kubono, Michitaro Kanamitsu, Kenji Koda, Takeshi Nakayama, Yasuhiro Kouro, Akira Hosogane, Natsuo Ajika, Kiyoteru Kobayashi

IEEE J. Solid State Circuits, 1999

1994

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.

Shin'ichi Kobayashi, Hiroaki Nakai, Yuichi Kunori, Takeshi Nakayama, Yoshikazu Miyawaki, Yasushi Terada, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

IEEE J. Solid State Circuits, April, 1994

1989

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs.

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Masanori Hayashikoshi, Yoshikazu Miyawaki, Natsuo Ajika, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara

IEEE J. Solid State Circuits, October, 1989