Natsuo Ajika
According to our database1,
Natsuo Ajika
authored at least 5 papers
between 1989 and 2017.
Collaborative distances:
Collaborative distances:
Timeline
1990
1995
2000
2005
2010
2015
0
1
2
1
1
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2017
IEEE J. Solid State Circuits, 2017
1999
A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications.
IEEE J. Solid State Circuits, 1999
1994
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.
IEEE J. Solid State Circuits, April, 1994
1992
A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories.
IEEE J. Solid State Circuits, April, 1992
1989
IEEE J. Solid State Circuits, October, 1989