Natsuki Kushiyama

According to our database, Natsuki Kushiyama authored at least 5 papers between 1991 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

A process-variation-tolerant dual-power-supply SRAM with 0.179µm² Cell in 40nm CMOS using level-programmable wordline driver.

Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

1999

A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme.

Satoru Takase, Natsuki Kushiyama

IEEE J. Solid State Circuits, 1999

1995

An experimental 295 MHz CMOS 4K⨉256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers.

Natsuki Kushiyama, Charles Tan, Richard Clark, Jane Lin, Fred Perner, Lisa Martin, Mark Leonard, Gene Coussens, Kit Cham

IEEE J. Solid State Circuits, November, 1995

1993

A 500-megabyte/s data-rate 4.5 M DRAM.

Natsuki Kushiyama, Shigeo Ohshima, Don Stark, Hiroyuki Noji, Kiyofumi Sakurai, Satoru Takase, Torhu Furuyama, Richard M. Barth, Andy Chan, John Dillon, James A. Gasbarro, Matthew M. Griffin, Mark Horowitz, Thomas H. Lee, Victor Lee

IEEE J. Solid State Circuits, April, 1993

1991

A 12 MHz data cycle 4 Mb DRAM with pipeline operation.

Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama, Tohru Furuyama

IEEE J. Solid State Circuits, April, 1991