Natesan Venkateswaran

According to our database, Natesan Venkateswaran authored at least 13 papers between 1996 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Radial basis function networks-based resource-aware offloading video analytics in mobile edge computing.

Jothi Prabha Appadurai, Prabaharan Sengodan, Natesan Venkateswaran, S. Abijah Roseline, B. Rama

Wirel. Networks, October, 2024

2016

Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains.

Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A distributed timing analysis framework for large designs.

Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran

Proceedings of the 53rd Annual Design Automation Conference, 2016

2012

Timing analysis with nonseparable statistical and deterministic variations.

Vladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Reversible statistical <i>max/min</i> operation: concept and applications to timing.

Debjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2006

First-Order Incremental Block-Based Statistical Timing Analysis.

Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Criticality computation in parameterized statistical timing.

Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah

Proceedings of the 43rd Design Automation Conference, 2006

2005

Gate sizing using incremental parameterized statistical timing analysis.

Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Optimization objectives and models of variation for statistical gate sizing.

Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

1999

Congestion Mitigation During Placement.

Kanad Chakraborty, Natesan Venkateswaran

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

Clock-skew constrained placement for row based designs.

Natesan Venkateswaran, Dinesh Bhatia

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

A constructive method for data path area estimation during high-level VLSI synthesis.

Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Clock-Skew Constrained Cell Placement.

Natesan Venkateswaran, Dinesh Bhatia

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996