Nastaran Nemati

According to our database, Nastaran Nemati authored at least 10 papers between 2009 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Clock-Less DFT-Less Test Strategy for Null Convention Logic.

Nastaran Nemati, Paul Beckett, Mark C. Reed, Karl M. Fant

IEEE Trans. Emerg. Top. Comput., 2018

2017

Test and Testability of Asynchronous Circuits.

Nastaran Nemati

PhD thesis, 2017

2016

Self-timed automatic test pattern generation for null convention logic.

Nastaran Nemati, Mark C. Reed, Sri Parameswaran, Karl M. Fant

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Asynchronous interleaved scan architecture for on-line built-in self-test of null convention logic.

Nastaran Nemati, Mark C. Reed, Karl M. Fant, Paul Beckett

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014

Asynchronous test hardware for Null Convention Logic.

Nastaran Nemati, Mark C. Reed, Michael R. Frater

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2011

Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing.

Nastaran Nemati, Zainalabedin Navabi

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Near optimal machine learning based random test generation.

Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

A mixed HDL/PLI test package.

Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Virtual tester development using HDL/PLI.

Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009

Optimizing Parametric BIST Using Bio-inspired Computing Algorithms.

Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009