Nasir Shaikh-Husin

Orcid: 0000-0001-8115-1270

According to our database1, Nasir Shaikh-Husin authored at least 21 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
High Throughput PRESENT Cipher Hardware Architecture for the Medical IoT Applications.
Cryptogr., March, 2023

2022
Accurate and compact convolutional neural network based on stochastic computing.
Neurocomputing, 2022

2021
Low-area and accurate inner product and digital filters based on stochastic computing.
Signal Process., 2021

CNTFET based Voltage Mode MISO Active only Biquadratic Filter for Multi-GHz Frequency Applications.
Circuits Syst. Signal Process., 2021

DPLBAnt: Improved load balancing technique based on detection and rerouting of elephant flows in software-defined networks.
Comput. Commun., 2021

2019
Accurate and compact stochastic computations by exploiting correlation.
Turkish J. Electr. Eng. Comput. Sci., 2019

Interleaved Incremental/Decremental Support Vector Machine for Embedded System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A linked list run-length-based single-pass connected component analysis for real-time embedded hardware.
J. Real Time Image Process., 2018

2017
Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms.
J. Syst. Archit., 2017

An optimized buffer insertion algorithm with delay-power constraints for VLSI layouts.
Turkish J. Electr. Eng. Comput. Sci., 2017

2016
FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application.
Int. J. Reconfigurable Comput., 2016

2015
Low cost pipelined FPGA architecture of Harris Corner Detector for real-time applications.
Proceedings of the Tenth International Conference on Digital Information Management, 2015

Sleep Apnea Event Detection System Based on Heart Rate Variability Analysis.
Proceedings of the Second International Conference on Advanced Data and Information Engineering, 2015

2014
Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip.
Appl. Comput. Intell. Soft Comput., 2014

An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Remote dynamically reconfigurable platform using NetFPGA.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Hardware transactional memory on multi-processor FPGA platform.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Feasible transition path generation for EFSM-based system testing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Network partitioning and GA heuristic crossover for NoC application mapping.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2010
A Particle Swarm Optimization Approach for Routing in VLSI.
Proceedings of the Second International Conference on Computational Intelligence, 2010

2002
Implementation of Recurrent Neural Network Algorithm for Shortest Path Calculation in Network Routing.
Proceedings of the International Symposium on Parallel Architectures, 2002


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