Nasim Pour Aryan

According to our database1, Nasim Pour Aryan authored at least 8 papers between 2012 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
Synthesis of DDRO Timing Monitors by Delay-Tracking and Static Timing Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2018
Design-dependent Monitors Based on Delay Sensitivity Tracking.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2016
In situ measurement of aging-induced performance degradation in digital circuits.
Proceedings of the 21th IEEE European Test Symposium, 2016

2014
Power efficient digital IC design for a medical application with high reliability requirements.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

From an analytic NBTI device model to reliability assessment of complex digital circuits.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013
Reliability monitoring of digital circuits by in situ timing measurement.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

2012
On-Line Supply voltage Scaling Based on <i>in situ</i> Delay Monitoring to Adapt for Pvta variations.
J. Circuits Syst. Comput., 2012

Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012


  Loading...