Naser Sedaghati

According to our database, Naser Sedaghati authored at least 16 papers between 2006 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures.

Payman Behnam, Naser Sedaghati, Mahdi Nazm Bojnordi

Proceedings of the 5th International Workshop on Energy Efficient Supercomputing, 2017

2016

EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures.

Renji Thomas, Naser Sedaghati, Radu Teodorescu

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Core tunneling: Variation-aware voltage noise mitigation in GPUs.

Renji Thomas, Kristin Barber, Naser Sedaghati, Li Zhou, Radu Teodorescu

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

A model-driven blocking strategy for load balanced sparse matrix-vector multiplication on GPUs.

Arash Ashari, Naser Sedaghati, John Eisenlohr, P. Sadayappan

J. Parallel Distributed Comput., 2015

Automatic Selection of Sparse Matrix Representation on GPUs.

Naser Sedaghati, Te Mu, Louis-Noël Pouchet, Srinivasan Parthasarathy, P. Sadayappan

Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

2014

On Using the Roofline Model with Lower Bounds on Data Movement.

Venmugil Elango, Naser Sedaghati, Fabrice Rastello, Louis-Noël Pouchet, J. Ramanujam, Radu Teodorescu, P. Sadayappan

ACM Trans. Archit. Code Optim., 2014

Fast Sparse Matrix-Vector Multiplication on GPUs for Graph Applications.

Arash Ashari, Naser Sedaghati, John Eisenlohr, Srinivasan Parthasarathy, P. Sadayappan

Proceedings of the International Conference for High Performance Computing, 2014

An efficient two-dimensional blocking strategy for sparse matrix-vector multiplication on GPUs.

Arash Ashari, Naser Sedaghati, John Eisenlohr, P. Sadayappan

Proceedings of the 2014 International Conference on Supercomputing, 2014

2012

Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips.

Timothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

StVEC: A Vector Instruction Extension for High Performance Stencil Computation.

Naser Sedaghati, Renji Thomas, Louis-Noël Pouchet, Radu Teodorescu, P. Sadayappan

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2008

An Efficient and Extendable Modeling Approach for VLIW DSP Processors.

Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Abbas Hormati, Sied Mehdi Fakhraie

Proceedings of the Advances in Computer Science and Engineering, 2008

2007

MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications.

Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Sied Mehdi Fakhraie

Proceedings of the 15th International Symposium on Modeling, 2007

Simulation of Voice Processing Applications through VLIW DSP Architectures.

Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Amin Farmahini Farahani, Mahmoud Mousavinezhad, Sied Mehdi Fakhraie

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Power efficient sequential multiplication using pre-computation.

Nima Honarmand, M. Reza Javaheri, Naser Sedaghati-Mokhtari, Ali Afzali-Kusha

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A High-Speed Low-Complexity VLSI SISO Architecture.

M. Nabipoor, S. A. Khodaian, Naser Sedaghati-Mokhtari, Sied Mehdi Fakhraie, Seyed Hamaidreza Jamali

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Efficient Self-Transposing Memory Structure for 32-bit Video Processors.

Mahdi Nazm Bojnordi, Naser Sedaghati-Mokhtari, Omid Fatemi, Mahmoud Reza Hashemi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006