Naser MohammadZadeh
Orcid: 0000-0002-7682-3455
According to our database1,
Naser MohammadZadeh
authored at least 28 papers
between 2007 and 2022.
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Bibliography
2022
AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Exact Mapping of Quantum Circuit Partitions to Building Blocks of the SAQIP Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2021
ACM Trans. Design Autom. Electr. Syst., 2021
A congestion-aware mixed integer linear programming model for placement and scheduling of quantum circuits with a two-level heuristic solution approach.
Quantum Eng., 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2019
ACM Trans. Archit. Code Optim., 2019
Qubit mapping of one-way quantum computation patterns onto 2D nearest-neighbor architectures.
Quantum Inf. Process., 2019
Anomaly Detection Using SVM as Classifier and Decision Tree for Optimizing Feature Vectors.
ISC Int. J. Inf. Secur., 2019
Proceedings of the 16th International ISC (Iranian Society of Cryptology) Conference on Information Security and Cryptology, 2019
2018
A power-performance tunable logic with adjustable threshold pseudo-dynamic building blocks and CMOS compatibility.
Int. J. Circuit Theory Appl., 2018
2017
Int. J. Circuit Theory Appl., 2017
2016
Microelectron. J., 2016
Microprocess. Microsystems, 2016
J. Inf. Sci. Eng., 2016
Proceedings of the 8th International Symposium on Telecommunications, 2016
Proceedings of the 8th International Symposium on Telecommunications, 2016
2015
An MINLP Model for Scheduling and Placement of Quantum Circuits with a Heuristic Solution Approach.
ACM J. Emerg. Technol. Comput. Syst., 2015
2014
Quantum Inf. Process., 2014
2011
Quantum Inf. Process., 2011
2010
Microelectron. J., 2010
2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model.
Microprocess. Microsystems, 2008
J. Circuits Syst. Comput., 2008
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems.
J. Comput. Syst. Sci., 2007
Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007