Narumi Sakashita
According to our database1,
Narumi Sakashita
authored at least 9 papers
between 1988 and 1999.
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Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
1999
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.
IEEE J. Solid State Circuits, 1999
1997
IEEE J. Solid State Circuits, 1997
Reduction of the Test Time for Mass Produced LSI Devices by Genetic Algorithms.
Proceedings of the Progress in Connectionist-Based Information Systems: Proceedings of the 1997 International Conference on Neural Information Processing and Intelligent Information Systems, 1997
1996
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.
IEEE J. Solid State Circuits, 1996
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
1990
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990
1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988