Naresh Sehgal

According to our database1, Naresh Sehgal authored at least 12 papers between 1994 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2003
Detailed Placement with Net Length Constraints.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

A novel ultra-fast heuristic for VLSI CAD steiner trees.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2001
Timing Driven Placement using Physical Net Constraints.
Proceedings of the 38th Design Automation Conference, 2001

2000
A novel technique for sea of gates global routing.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A sensitivity based placer for standard cells.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
Extraction of functional regularity in datapath circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998
Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A general approach for regularity extraction in datapath circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1995
Power conscious CAD tools and methodologies: a perspective.
Proc. IEEE, 1995

1994
An object-oriented cell library manager.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A gridless multi-layer area router.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994


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