Naresh Maheshwari

According to our database, Naresh Maheshwari authored at least 7 papers between 1996 and 1999.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1999

Optimizing large multiphase level-clocked circuits.

Naresh Maheshwari, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Retiming control logic.

Naresh Maheshwari, Sachin S. Sapatnekar

Integr., 1999

1998

Efficient retiming of large circuits.

Naresh Maheshwari, Sachin S. Sapatnekar

IEEE Trans. Very Large Scale Integr. Syst., 1998

Efficient Minarea Retiming of Large Level-Clocked Circuits.

Naresh Maheshwari, Sachin S. Sapatnekar

Proceedings of the 1998 Design, 1998

1997

Minimum area retiming with equivalent initial states.

Naresh Maheshwari, Sachin S. Sapatnekar

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

An Improved Algorithm for Minimum-Area Retiming.

Naresh Maheshwari, Sachin S. Sapatnekar

Proceedings of the 34st Conference on Design Automation, 1997

1996

A Practical Algorithm for Retiming Level-Clocked Circuits.

Naresh Maheshwari, Sachin S. Sapatnekar

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996