Narendra V. Shenoy

According to our database, Narendra V. Shenoy authored at least 34 papers between 1990 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

On Efficient and Robust Constraint Generation for Practical Layout Legalization.

Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Cell Swapping Based Migration Methodology for Analog and Custom Layouts.

Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Advances in Computation of the Maximum of a Set of Gaussian Random Variables.

Debjit Sinha, Hai Zhou, Narendra V. Shenoy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.

Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Statistical Timing Yield Optimization by Gate Sizing.

Debjit Sinha, Narendra V. Shenoy, Hai Zhou

IEEE Trans. Very Large Scale Integr. Syst., 2006

Advances in Computation of the Maximum of a Set of Random Variables.

Debjit Sinha, Hai Zhou, Narendra V. Shenoy

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

Statistical gate sizing for timing yield optimization.

Debjit Sinha, Narendra V. Shenoy, Hai Zhou

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables.

Shabbir H. Batterywala, Narendra V. Shenoy

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Design automation for mask programmable fabrics.

Narendra V. Shenoy, Jamil Kawa, Raul Camposano

Proceedings of the 41th Design Automation Conference, 2004

2003

A Method to Estimate Slew and Delay in Coupled Digital Circuits.

Shabbir H. Batterywala, Narendra V. Shenoy

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Emerging markets: design goes global.

Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei

Proceedings of the 40th Design Automation Conference, 2003

2002

Efficient minimum spanning tree construction without Delaunay triangulation.

Hai Zhou, Narendra V. Shenoy, William Nicholls

Inf. Process. Lett., 2002

An Efficient External-Memory Implementation of Region Query with Application to Area Routing.

Stan Y. Liao, Narendra V. Shenoy, William Nicholls

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Track assignment: a desirable intermediate step between global routing and detailed routing.

Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

An efficient routing database.

Narendra V. Shenoy, William Nicholls

Proceedings of the 39th Design Automation Conference, 2002

2001

Timing Analysis with Crosstalk as Fixpoints on Complete Lattice.

Hai Zhou, Narendra V. Shenoy, William Nicholls

Proceedings of the 38th Design Automation Conference, 2001

1999

A Robust Solution to the Timing Convergence Problem in High-Performance Design.

Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking

Proceedings of the IEEE International Conference On Computer Design, 1999

1997

Retiming: Theory and practice.

Narendra V. Shenoy

Integr., 1997

The future of logic synthesis and physical design in deep-submicron process geometries.

Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy

Proceedings of the 1997 International Symposium on Physical Design, 1997

Discrete Drive Selection for Continuous Sizing.

Ramsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

Embedded tutorial: Speed - new paradigms in design for performance.

Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Functional clock schedule optimization.

Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994

Linear programming for hazard elimination in asynchronous circuits.

Luciano Lavagno, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli

J. VLSI Signal Process., 1994

Efficient implementation of retiming.

Narendra V. Shenoy, Richard L. Rudell

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Minimum padding to satisfy short path constraints.

Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Resynthesis of Multi-Phase Pipelines.

Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 30th Design Automation Conference. Dallas, 1993

A Verification Technique for Gated Clock.

Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Verifying clock schedules.

Thomas G. Szymanski, Narendra V. Shenoy

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Graph algorithms for clock schedule optimization.

Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

On the Temporal Equivalence of Sequential Circuits.

Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 29th Design Automation Conference, 1992

1991

Retiming of Circuits with Single Phase Transparent Latches.

Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Performance Directed Synthesis for Table Look Up Programmable Gate Arrays.

Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Improved Logic Synthesis Algorithms for Table Look Up Architectures.

Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990

Logic Synthesis for Programmable Gate Arrays.

Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990