Narender Hanchate

According to our database, Narender Hanchate authored at least 10 papers between 2004 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Improving Chip Design Performance and Productivity Using Machine Learning.

Narender Hanchate

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2007

Statistical Gate Sizing for Yield Enhancement at Post Layout Level.

Narender Hanchate, Nagarajan Ranganathan

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Integrated Gate and Wire Sizing at Post Layout Level.

Narender Hanchate, Nagarajan Ranganathan

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing.

Narender Hanchate, Nagarajan Ranganathan

ACM Trans. Design Autom. Electr. Syst., 2006

Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory.

Narender Hanchate, Nagarajan Ranganathan

IEEE Trans. Computers, 2006

A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.

Narender Hanchate, Nagarajan Ranganathan

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL.

Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization.

Narender Hanchate, Nagarajan Ranganathan

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2004

LECTOR: a technique for leakage reduction in CMOS circuits.

Narender Hanchate, Nagarajan Ranganathan

IEEE Trans. Very Large Scale Integr. Syst., 2004

A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.

Narender Hanchate, Nagarajan Ranganathan

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004