Naran Sirisantana
According to our database1,
Naran Sirisantana
authored at least 10 papers
between 2000 and 2005.
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Bibliography
2005
2004
IEEE Des. Test Comput., 2004
2003
A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies.
Proceedings of the ESSCIRC 2003, 2003
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
2001
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
2000
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000