Naoyuki Kawabe
According to our database1,
Naoyuki Kawabe
authored at least 11 papers
between 2000 and 2018.
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Bibliography
2018
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC.
IEEE J. Solid State Circuits, 2018
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2007
Proceedings of the 25th International Conference on Computer Design, 2007
2006
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.
IEEE J. Solid State Circuits, 2006
2005
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction.
Proceedings of the 2005 Design, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2002
J. Circuits Syst. Comput., 2002
Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
2000
Proceedings of the 37th Conference on Design Automation, 2000
Low-power technique for on-chip memory using biased partitioning and access concentration.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000