Naoya Tokiwa
According to our database1,
Naoya Tokiwa
authored at least 9 papers
between 2002 and 2021.
Collaborative distances:
Collaborative distances:
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Bibliography
2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2012
IEEE J. Solid State Circuits, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
A 56-nm CMOS 99-mm<sup>2</sup> 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput.
IEEE J. Solid State Circuits, 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2002
A 44-mm<sup>2</sup> four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller.
IEEE J. Solid State Circuits, 2002