Naoya Niwa

Orcid: 0000-0002-9695-4858

According to our database1, Naoya Niwa authored at least 9 papers between 2018 and 2024.

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Bibliography

2024
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024

2023
A Compression Router for Low-Latency Network-on-Chip.
IEICE Trans. Inf. Syst., February, 2023

2022
Boosting the Performance of Interconnection Networks by Selective Data Compression.
IEICE Trans. Inf. Syst., December, 2022

Distance Aware Compression for Low Latency High Bandwidth Interconnection Network.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

2021
A Case for Low-Latency Network-on-Chip using Compression Routers.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2019
The Case for Water-Immersion Computer Boards.
Proceedings of the 48th International Conference on Parallel Processing, 2019

Sparse 3-D NoCs with Inductive Coupling.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018


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