Naoya Nakayama

According to our database, Naoya Nakayama authored at least 2 papers between 2008 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2010

Full Chip Circuit/Substrate Macro Modeling Method Which Controls the Analysis Accuracy and CPU Time by Using Current Density.

Mikiko Sode Tanaka, Mikihiro Kajita, Naoya Nakayama, Satoshi Nakamoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2008

A method using circuit/substrate macro modeling to analyze substrate noise in a 3.2-GHz 350M-transistor microprocessor.

Mikiko Sode Tanaka, Mikihiro Kajita, Naoya Nakayama, Satoshi Nakamoto

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008