Naotaka Hashimoto

According to our database, Naotaka Hashimoto authored at least 5 papers between 1989 and 1995.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1995

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.

Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida

IEEE J. Solid State Circuits, April, 1995

1994

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers.

Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki

IEEE J. Solid State Circuits, April, 1994

1993

A 16-Mb CMOS SRAM with a 2.3- mu m² single-bit-line memory cell.

Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki

IEEE J. Solid State Circuits, November, 1993

1992

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier.

Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu

IEEE J. Solid State Circuits, November, 1992

1989

A 9-ns 1-Mbit CMOS SRAM.

Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo

IEEE J. Solid State Circuits, October, 1989