Naoki Terao

According to our database, Naoki Terao authored at least 4 papers between 2016 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

An over 220-GHz-Bandwidth Distributed Active Power Combiner in 250-nm InP DHBT.

Teruo Jyo, Munehiko Nagatani, Minoru Ida, Miwa Mutoh, Hitoshi Wakita, Naoki Terao, Hideyuki Nosaka

Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020

2018

Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment.

Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada

J. Electron. Test., 2018

2017

Extension of power supply impedance emulation method on ATE for multiple power domain.

Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada

Proceedings of the 22nd IEEE European Test Symposium, 2017

2016

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board.

Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada

Proceedings of the 2016 IEEE International Test Conference, 2016