Naoki Kuroda

According to our database, Naoki Kuroda authored at least 4 papers between 1995 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2005

A 400-MHz random-cycle dual-port interleaved DRAM (D²RAM) with standard CMOS Process.

Masanori Shirahama, Yasuhiro Agata, Toshiaki Kawasaki, Ryuji Nishihara, Wataru Abe, Naoki Kuroda, Hiroyuki Sadakata, Toshitaka Uchikoba, Kazunari Takahashi, Kyoko Egashira, Shinji Honda, Miho Miura, Shin Hashimoto, Hirohito Kikukawa, Hiroyuki Yamauchi

IEEE J. Solid State Circuits, 2005

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning.

Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto

IEEE J. Solid State Circuits, 2005

2000

An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D²/RAM).

Yasuhiro Agata, Kenji Motomochi, Yoshifumi Fukushima, Masanori Shirahama, Marefusa Kurumada, Naoki Kuroda, Hiroyuki Sadakata, Kohtaro Hayashi, Toshio Yamada, Kazunari Takahashi, Tsutomu Fujita

IEEE J. Solid State Circuits, 2000

1995

Error Spectrum Shaping in 2-D Digital Filters.

Takao Hinamoto, Shuji Karino, Naoki Kuroda

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995