Naoki Kitai

According to our database1, Naoki Kitai authored at least 8 papers between 1999 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2007
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme.
IEEE J. Solid State Circuits, 2005

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

1999
PLL synthesizer with multi-programmable divider and multi-phase detector.
IEEE Trans. Consumer Electron., 1999

PLL frequency synthesizer with an auxiliary programmable divider.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Dead-zone-less PLL frequency synthesizer by hybrid phase detectors.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Performance improvement in a binary phase comparator type PLL frequency synthesizer.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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