Naoki Kasai

According to our database1, Naoki Kasai authored at least 13 papers between 1992 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1995
2000
2005
2010
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1
2
3
4
2
3
2
1
1
2
1
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Legend:

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In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2009
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs.
IEEE J. Solid State Circuits, 2009

Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros.
IEICE Trans. Electron., 2009


2007
A 16-Mb Toggle MRAM With Burst Modes.
IEEE J. Solid State Circuits, 2007

MRAM Applications Using Unlimited Write Endurance.
IEICE Trans. Electron., 2007

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode.
IEICE Trans. Electron., 2007

2005
Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs.
IEICE Trans. Electron., 2005

Special Section on Microelectronic Test Structures.
IEICE Trans. Electron., 2005

2001
FeRAM device and circuit technologies fully compatible with advanced CMOS.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1993
A 30-ns 256-Mb DRAM with a multidivided array structure.
IEEE J. Solid State Circuits, November, 1993

1992
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function.
IEEE J. Solid State Circuits, November, 1992


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