Naofumi Takagi

According to our database, Naofumi Takagi authored at least 89 papers between 1982 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor.

Takahiro Kawaguchi, Naofumi Takagi

IEICE Trans. Electron., 2022

2021

Zytlebot : FPGA integrated ros-based autonomous mobile robot.

Ryota Miyagi, Naofumi Takagi, Sho Kinoshista, Masashi Oda, Hideki Takase

Proceedings of the International Conference on Field-Programmable Technology, 2021

2020

mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices.

Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi

J. Inf. Process., 2020

2019

Concurrent Error Detectable Carry Select Adder with Easy Testability.

Nobutaka Kito, Naofumi Takagi

IEEE Trans. Computers, 2019

Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses.

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi

IPSJ Trans. Syst. LSI Des. Methodol., 2019

mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices.

Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

2018

Algorithms for Evaluating the Matrix Polynomial <i>I</i>+<i>A</i>+<i>A</i>²+...+<i>A</i>^<i>N</i>-1 with Reduced Number of Matrix Multiplications.

Kotaro Matsumoto, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress.

Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the International Conference on Embedded Software, 2018

2017

Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication.

Nobutaka Kito, Kazushi Akimoto, Naofumi Takagi

IEICE Trans. Inf. Syst., 2017

Recap of the 22nd Asia and South- Pacific Design Automation Conference.

Naofumi Takagi

IEEE Des. Test, 2017

2016

RSFQ 4-bit Bit-Slice Integer Multiplier.

Guang-Ming Tang, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2016

High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation.

Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2016

An evaluation framework of OS-level power managements for the big.LITTLE architecture.

Hideki Takase, Kazumi Aono, Yutaka Matsubara, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015

An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems.

Takuya Hatayama, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi

IPSJ Trans. Syst. LSI Des. Methodol., 2015

A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model.

Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

2014

Circuit Description and Design Flow of Superconducting SFQ Logic Circuits.

Kazuyoshi Takagi, Nobutaka Kito, Naofumi Takagi

IEICE Trans. Electron., 2014

Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis.

Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm² Nb Process.

Xizhu Peng, Yuki Yamanashi, Nobuyuki Yoshikawa, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi, Mutsuo Hidaka

IEICE Trans. Electron., 2014

Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation.

Shuichi Nagasawa, Kenji Hinode, Tetsuro Satoh, Mutsuo Hidaka, Hiroyuki Akaike, Akira Fujimaki, Nobuyuki Yoshikawa, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2014

A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits.

Hiroshi Kataoka, Hiroaki Honda, Farhad Mehdipour, Nobuyuki Yoshikawa, Akira Fujimaki, Hiroyuki Akaike, Naofumi Takagi, Kazuaki J. Murakami

IEICE Trans. Electron., 2014

Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors.

Akira Fujimaki, Masamitsu Tanaka, Ryo Kasagi, Katsumi Takagi, Masakazu Okada, Yuhi Hayakawa, Kensuke Takata, Hiroyuki Akaike, Nobuyuki Yoshikawa, Shuichi Nagasawa, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2014

An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality.

Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication.

Nobutaka Kito, Naofumi Takagi

IEICE Trans. Inf. Syst., 2013

A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis.

Akihiro Suda, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

2012

Fast inversion algorithm in GF(2^m) suitable for implementation with a polynomial multiply instruction on GF(2).

Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi

IET Comput. Digit. Tech., 2012

A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition.

Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2012

A C-Testable Multiple-Block Carry Select Adder.

Nobutaka Kito, Shinichi Fujii, Naofumi Takagi

IEICE Trans. Inf. Syst., 2012

2011

Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers.

Hirotaka Kawashima, Naofumi Takagi

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits.

Kazuyoshi Takagi, Yuki Ito, Shota Takeshima, Masamitsu Tanaka, Naofumi Takagi

IEICE Trans. Electron., 2011

2010

100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm² Nb Multi-Layer Process.

Yuki Yamanashi, Toshiki Kainuma, Nobuyuki Yoshikawa, Irina Kataeva, Hiroyuki Akaike, Akira Fujimaki, Masamitsu Tanaka, Naofumi Takagi, Shuichi Nagasawa, Mutsuo Hidaka

IEICE Trans. Electron., 2010

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm.

Masamitsu Tanaka, Koji Obata, Yuki Ito, Shota Takeshima, Motoki Sato, Kazuyoshi Takagi, Naofumi Takagi, Hiroyuki Akaike, Akira Fujimaki

IEICE Trans. Electron., 2010

Comparisons of Synchronous-Clocking SFQ Adders.

Naofumi Takagi, Masamitsu Tanaka

IEICE Trans. Electron., 2010

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing.

Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Inf. Syst., 2010

A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier.

Nobutaka Kito, Kensuke Hanai, Naofumi Takagi

IEICE Trans. Inf. Syst., 2010

2009

Fast Hardware Algorithm for Division in hbox 2^m Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions.

Katsuki Kobayashi, Naofumi Takagi

IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008

A Combined Circuit for Multiplication and Inversion in GF(2^m).

Katsuki Kobayashi, Naofumi Takagi

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Bipartite Modular Multiplication Method.

Marcelo E. Kaihara, Naofumi Takagi

IEEE Trans. Computers, 2008

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits.

Naofumi Takagi, Kazuaki J. Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda

IEICE Trans. Electron., 2008

A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits.

Koji Obata, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems.

Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Level-Testability of Multi-operand Adders.

Nobutaka Kito, Naofumi Takagi

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits.

Koji Obata, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Electron., 2007

Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams.

Koji Obata, Kazuyoshi Takagi, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2).

Katsuki Kobayashi, Naofumi Takagi, Kazuyoshi Takagi

Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2006

A Hardware Algorithm for Integer Division Using the SD2 Representation.

Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Hardware Algorithm for Computing Reciprocal of Euclidean Norm of a 3-D Vector.

Fumio Kumazawa, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2005

A Hardware Algorithm for Modular Multiplication/Division.

Marcelo E. Kaihara, Naofumi Takagi

IEEE Trans. Computers, 2005

A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm.

Marcelo E. Kaihara, Naofumi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Bipartite Modular Multiplication.

Marcelo E. Kaihara, Naofumi Takagi

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

A Hardware Algorithm for Integer Division.

Naofumi Takagi, Shunsuke Kadowaki, Kazuyoshi Takagi

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004

Systematic IEEE rounding method for high-speed floating-point multipliers.

Nhon T. Quach, Naofumi Takagi, Michael J. Flynn

IEEE Trans. Very Large Scale Integr. Syst., 2004

2003

Digit-Recurrence Algorithm for Computing Reciprocal Square-Root.

Naofumi Takagi, Daisuke Matsuoka, Kazuyoshi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A VLSI Algorithm for Modular Multiplication/Division.

Marcelo E. Kaihara, Naofumi Takagi

Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002

A VLSI Algorithm for Division in GF(2^m) Based on Extended Binary GCD Algorithm.

Yasuaki Watanabe, Naofumi Takagi, Kazuyoshi Takagi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Special Session: Security on SoC.

Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms.

Naofumi Takagi

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2001

A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis.

Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi

IEEE Trans. Computers, 2001

A Hardware Algorithm for Computing Reciprocal Square Root.

Naofumi Takagi

Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000

A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector.

Naofumi Takagi, Seiji Kuwahara

IEEE Trans. Computers, 2000

A fast addition algorithm for elliptic curve arithmetic in GF(2ⁿ) using projective coordinates.

Akira Higuchi, Naofumi Takagi

Inf. Process. Lett., 2000

1999

Adders.

Naofumi Takagi, Haruyuki Tago, Charles R. Baugh, Saburo Muroga

Proceedings of the VLSI Handbook., 1999

Dividers.

Naofumi Takagi, Saburo Muroga

Proceedings of the VLSI Handbook., 1999

Multipliers.

Naofumi Takagi, Charles R. Baugh, Saburo Muroga

Proceedings of the VLSI Handbook., 1999

A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival.

Naofumi Takagi, Takashi Horiyama

IEEE Trans. Computers, 1999

Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector.

Naofumi Takagi, Seiji Kuwahara

Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998

Powering by a Table Look-Up and a Multiplication with Operand Modification.

Naofumi Takagi

IEEE Trans. Computers, 1998

1997

Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification.

Masayuki Ito, Naofumi Takagi, Shuzo Yajima

IEEE Trans. Computers, 1997

O(n)-Depth Modular Exponentiation Circuit Algorithm.

Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata

IEEE Trans. Computers, 1997

Generating a Power of an Operand by a Table Look-up and a Multiplication.

Naofumi Takagi

Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1996

Square Rooting by Iterative Multiply-Additions.

Masayuki Ito, Naofumi Takagi, Shuzo Yajima

Inf. Process. Lett., 1996

1995

A Multiple-Precision Modular Multiplication Algorithm with Triangle Additions.

Naofumi Takagi

IEICE Trans. Inf. Syst., 1995

Efficient Initial Approximation and Fast Converging Methods for Division and Square Root.

Masayuki Ito, Naofumi Takagi, Shuzo Yajima

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

Function Evaluation by Table Look-up and Addition.

Hannes Hassler, Naofumi Takagi

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

O(n)-depth circuit algorithm for modular exponentiation.

Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1993

A modular multiplication algorithm with triangle additions.

Naofumi Takagi

Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1992

Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem.

Naofumi Takagi, Shuzo Yajima

IEEE Trans. Computers, 1992

A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation.

Naofumi Takagi

IEEE Trans. Computers, 1992

1991

Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation.

Naofumi Takagi, Tohru Asada, Shuzo Yajima

IEEE Trans. Computers, 1991

An on-line error-detectable high-speed array divider.

Naofumi Takagi, Shuzo Yajima

Syst. Comput. Jpn., 1991

A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications.

Naofumi Takagi

Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

1988

An on-line error-detectable array divider with a redundant binary representation and a residue code.

Naofumi Takagi, Shuzo Yajima

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987

On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic.

Naofumi Takagi, Shuzo Yajima

IEEE Trans. Computers, 1987

On high-speed parallel algorithms using redundant coding.

Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima

Syst. Comput. Jpn., 1987

A hardware algorithm for computing sine and cosine using redundant binary representation.

Naofumi Takagi, Tohru Asada, Shuzo Yajima

Syst. Comput. Jpn., 1987

Design of high speed MOS multiplier and divider using redundant binary representation.

Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi

Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1986

Hardware algorithms for computing exponentials and logarithms using redundant binary representation.

Naofumi Takagi, Shuzo Yajima

Syst. Comput. Jpn., 1986

A square root hardware algorithm using redundant binary representation.

Naofumi Takagi, Shuzo Yajima

Syst. Comput. Jpn., 1986

1985

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.

Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima

IEEE Trans. Computers, 1985

1982

The Parallel Enumeration Sorting Scheme for VLSI.

Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima

IEEE Trans. Computers, 1982