Naofumi Homma

IACR Cryptol. ePrint Arch., 2024

Side-Channel Linearization Attack on Unrolled Trivium Hardware.

[BibT_eX]

[DOI]

IACR Commun. Cryptol., 2024

Comparative Analysis and Implementation of Jump Address Masking for Preventing TEE Bypassing Fault Attacks.

[BibT_eX]

[DOI]

Shoei Nashimoto

Proceedings of the 19th International Conference on Availability, Reliability and Security, 2024

2023

Side-Channel Analysis Against SecOC-Compliant AES-CMAC.

[BibT_eX]

[DOI]

Katsumi Ebina

IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

Homomorphic encryption for stochastic computing.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., June, 2023

How Secure is Exponent-blinded RSA-CRT with Sliding Window Exponentiation?

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Multiple-Valued Plaintext-Checking Side-Channel Attacks on Post-Quantum KEMs.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

Crystalor: Persistent Memory Encryption Mechanism with Optimized Metadata Structure and Fast Crash Recovery.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

Formal Analysis of Non-profiled Deep-learning Based Side-channel Attacks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

Efficient DFA-Resistant AES Hardware Based on Concurrent Fault Detection Scheme.

[BibT_eX]

[DOI]

Yusuke Yagyu

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

2022

ELM: A Low-Latency and Scalable Memory Encryption Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2022

Curse of Re-encryption: A Generic Power/EM Analysis on Post-Quantum KEMs.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

One Truth Prevails: A Deep-learning Based Single-Trace Power Analysis on RSA-CRT with Windowed Exponentiation.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Perceived Information Revisited New Metrics to Evaluate Success Rate of Side-Channel Attacks.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

AES S-Box Hardware With Efficiency Improvement Based on Linear Mapping Optimization.

[BibT_eX]

[DOI]

Ayano Nakashima

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

On the Success Rate of Side-Channel Attacks on Masked Implementations: Information-Theoretical Bounds and Their Practical Usage.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

High-Speed Hardware Architecture for Post-Quantum Diffie-Hellman Key Exchange Based on Residue Number System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber.

[BibT_eX]

[DOI]

Yuma Itabashi

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

Imbalanced Data Problems in Deep Learning-Based Side-Channel Attacks: Analysis and Solution.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2021

A method for constructing sliding windows leak from noisy cache timing information.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2021

An Algebraic Approach to Verifying Galois-Field Arithmetic Circuits with Multiple-Valued Characteristics.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2021

Fault-Injection Attacks against NIST's Post-Quantum Cryptography Round 3 KEM Candidates.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

Toward Optimal Deep-Learning Based Side-Channel Attacks: Probability Concentration Inequality Loss and Its Usage.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

A Formal Approach to Identifying Hardware Trojans in Cryptographic Hardware.

[BibT_eX]

[DOI]

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

Extraction of Binarized Neural Network Architecture and Secret Parameters Using Side-Channel Information.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Rejection Sampling Schemes for Extracting Uniform Distribution from Biased PUFs.

[BibT_eX]

[DOI]

Kohei Kazumori

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Unified Hardware for High-Throughput AES-Based Authenticated Encryptions.

[BibT_eX]

[DOI]

Shotaro Sawataishi

IEEE Trans. Circuits Syst. II Express Briefs, 2020

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Bypassing Isolated Execution on RISC-V with Fault Injection.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Debiasing Method for Efficient Ternary Fuzzy Extractors and Ternary Physically Unclonable Functions.

[BibT_eX]

[DOI]

Kohei Kazumori

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Effective Formal Verification for Galois-field Arithmetic Circuits with Multiple-Valued Characteristics.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

PMAC++: Incremental MAC Scheme Adaptable to Lightweight Block Ciphers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Single-Trace Side-Channel Analysis on Polynomial-Based MAC Schemes.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020

Practical Side-Channel Based Model Extraction Attack on Tree-Based Machine Learning Algorithm.

[BibT_eX]

[DOI]

Proceedings of the Applied Cryptography and Network Security Workshops, 2020

2019

Efficient Fuzzy Extractors Based on Ternary Debiasing Method for Biased Physically Unclonable Functions.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Tackling Biased PUFs Through Biased Masking: A Debiasing Method for Efficient Fuzzy Extractor.

[BibT_eX]

[DOI]

Manami Suzuki

IEEE Trans. Computers, 2019

Highly efficient GF(2<sup>8</sup>) inversion circuit based on hybrid GF representations.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2019

Introduction to Electromagnetic Information Security.

[BibT_eX]

[DOI]

Yu-ichi Hayashi

IEICE Trans. Commun., 2019

Constructing Sliding Windows Leak from Noisy Cache Timing Information of OSS-RSA.

[BibT_eX]

[DOI]

Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019

A Ternary Fuzzy Extractor for Efficient Cryptographic Key Generation.

[BibT_eX]

[DOI]

Kohei Kazumori

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

High Throughput/Gate FN-Based Hardware Architectures for AES-OTR.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Introduction to the CHES 2017 special issue.

[BibT_eX]

[DOI]

Wieland Fischer

J. Cryptogr. Eng., 2018

Characterizing Parallel Multipliers for Detecting Hardware Trojans.

[BibT_eX]

[DOI]

FLAP, 2018

Side-channel-aware LSI design.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Quaternary Debiasing for Physically Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

On the Detectability of Hardware Trojans Embedded in Parallel Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

On Masked Galois-Field Multiplication for Authenticated Encryption Resistant to Side Channel Analysis.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2018

A Non-Reversible Insertion Method for Hardware Trojans Based on Path Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the PROOFS 2018, 2018

2017

Formal Approach for Verifying Galois Field Arithmetic Circuits of Higher Degrees.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks.

[BibT_eX]

[DOI]

J. Cryptol., 2017

Buffer overflow attack with multiple fault injection and a proven countermeasure.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2017

Introduction to the PROOFS 2016 special section.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2017

Power Analysis on Unrolled Architecture with Points-of-Interest Search and Its Application to PRINCE Block Cipher.

[BibT_eX]

[DOI]

Ville Yli-Mäyry

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Hierarchical Formal Verification Combining Algebraic Transformation with PPRM Expansion and Its Application to Masked Cryptographic Processors.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Automatic Generation System for Multiple-Valued Galois-Field Parallel Multipliers.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

Protecting cryptographic integrated circuits with side-channel information.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Fault Injection Attack on Salsa20 and ChaCha and a Lightweight Countermeasure.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

Chosen-input side-channel analysis on unrolled light-weight cryptographic hardware.

[BibT_eX]

[DOI]

Ville Yli-Mäyry

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares.

[BibT_eX]

[DOI]

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Practical Power Analysis on KCipher-2 Software on Low-End Microcontrollers.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE European Symposium on Security and Privacy Workshops, 2017

Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Toward More Efficient DPA-Resistant AES Hardware Architecture Based on Threshold Implementation.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017

Multiple-Valued Debiasing for Physically Unclonable Functions and Its Application to Fuzzy Extractors.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017

2016

A Formal Verification Method of Error Correction Code Processors Over Galois-Field Arithmetic.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2016

A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors.

[BibT_eX]

[DOI]

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015

A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Formal Approach to Designing Multiple-Valued Arithmetic Circuits.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2015

Electromagnetic Analysis against Public-Key Cryptographic Software on Embedded OS.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2015

Efficient DFA on SPN-Based Block Ciphers and Its Application to the LED Block Cipher.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

An Adaptive Multiple-Fault Injection Attack on Microcontrollers and a Countermeasure.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Highly Efficient GF(2<sup>8</sup>) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Improved Power Analysis on Unrolled Architecture and Its Application to PRINCE Block Cipher.

[BibT_eX]

[DOI]

Ville Yli-Mäyry

Proceedings of the Lightweight Cryptography for Security and Privacy, 2015

Formal Design of Galois-Field Arithmetic Circuits Based on Polynomial Ring Representation.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

System for Automatic Generation of Parallel Multipliers over Galois Fields.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

EM attack sensor: concept, circuit, and design-automation methodology.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Toward Formal Design of Practical Cryptographic Hardware Based on Galois Field Arithmetic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Practical DFA Strategy for AES Under Limited-access Conditions.

[BibT_eX]

[DOI]

J. Inf. Process., 2014

Formal Design of Arithmetic Circuits over Galois Fields Based on Normal Basis Representations.

[BibT_eX]

[DOI]

Kotaro Okamoto

IEICE Trans. Inf. Syst., 2014

Chosen-IV Correlation Power Analysis on KCipher-2 Hardware and a Masking-Based Countermeasure.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.

[BibT_eX]

[DOI]

Pirouz Bazargan-Sabet

Shivam Bhasin

Jean-Luc Danger

IEICE Trans. Electron., 2014

EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2014

A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2014

An Efficient Approach to Verifying Galois-Field Arithmetic Circuits of Higher Degrees and Its Application to ECC Decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

A hierarchical formal approach to verifying side-channel resistant cryptographic processors.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Side-channel leakage on silicon substrate of CMOS cryptographic chip.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

A Multiple-Fault Injection Attack by Adaptive Timing Control Under Black-Box Conditions and a Countermeasure.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014

A Threat for Tablet PCs in Public Space: Remote Visualization of Screen Images Using EM Emanation.

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications Security, 2014

2013

A Graph-Based Approach to Designing Parallel Multipliers over Galois Fields Based on Normal Basis Representations.

[BibT_eX]

[DOI]

Kotaro Okamoto

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Yet Another Fault-Based Leakage in Non-uniform Faulty Ciphertexts.

[BibT_eX]

[DOI]

Proceedings of the Foundations and Practice of Security - 6th International Symposium, 2013

Transient analysis of EM radiation associated with information leakage from cryptographic ICs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

Exploring the Relations between Fault Sensitivity and Power Consumption.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2013

Chosen-IV Correlation Power Analysis on KCipher-2 and a Countermeasure.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2013

2012

Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Formal Approach to Designing Cryptographic Processors Based on $GF(2^m)$ Arithmetic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2012

Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Effective data processing and protection techniques for community network nodes.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on Wireless Personal Multimedia Communications, 2012

Formal Design of Multiple-Valued Arithmetic Algorithms over Galois Fields and Its Application to Cryptographic Processor.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Security Evaluation of Cryptographic Modules against Profiling Attacks.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - ICISC 2012, 2012

An Efficient Countermeasure against Fault Sensitivity Analysis Using Configurable Delay Blocks.

[BibT_eX]

[DOI]

Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012

2011

Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

An on-chip glitchy-clock generator for testing fault injection attacks.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2011

High-Performance Architecture for Concurrent Error Detection for AES Processors.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A Graph-Based Approach to Designing Multiple-Valued Arithmetic Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Comparative Power Analysis of Modular Exponentiation Algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

Profiling attack using multivariate regression analysis.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2010

Design of Tamper-Resistant Registers for Multiple-Valued Cryptographic Processors.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

Hardware Implementations of Hash Function Luffa.

[BibT_eX]

[DOI]

Proceedings of the HOST 2010, 2010

2009

Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2009

Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules.

[BibT_eX]

[DOI]

Proceedings of the Information Security Applications, 10th International Workshop, 2009

Multiple-Valued Constant-Power Adder for Cryptographic Processors.

[BibT_eX]

[DOI]

Proceedings of the ISMVL 2009, 2009

Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Differential power analysis of AES ASIC implementations with various S-box circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Development of side-channel attack standard evaluation environment.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

Arithmetic Circuit Verification Based on Symbolic Computer Algebra.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool.

[BibT_eX]

[DOI]

Proceedings of the Information Security Applications, 9th International Workshop, 2008

Enhanced Correlation Power Analysis Using Key Screening Technique.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Arithmetic module generator with algorithm optimization capability.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

High-performance ASIC implementations of the 128-bit block cipher CLEFIA.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Enhanced power analysis attack using chosen message against RSA hardware implementations.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Systematic design of high-radix Montgomery multipliers for RSA processors.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Chosen-message SPA attacks against FPGA-based RSA hardware implementations.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

High-Performance Concurrent Error Detection Scheme for AES Hardware.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems, 2008

Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems, 2008

2007

Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2007

Synthesis of current mirrors based on evolutionary graph generation with transmigration capability.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2007

Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Application of symbolic computer algebra to arithmetic circuit verification.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Computer Design, 2007

2006

Formal Design of Arithmetic Circuits Based on Arithmetic Description Language.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2006

Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

2005

Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2005

2004

Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation.

[BibT_eX]

[DOI]

Proceedings of the Parallel Problem Solving from Nature, 2004

Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

A systematic approach for analyzing fast addition algorithms using counter tree diagrams.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Multiplier Block Synthesis Using Evolutionary Graph Generation.

[BibT_eX]

[DOI]

Proceedings of the 6th NASA / DoD Workshop on Evolvable Hardware (EH 2004), 2004

2003

Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Evolutionary Synthesis of Arithmetic Circuit Structures.

[BibT_eX]

[DOI]

Artif. Intell. Rev., 2003

A framework of evolutionary graph generation system and its application to circuit synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

VLSI circuit design using an object-oriented framework of evolutionary graph generation system.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2003

2002

Graph-based evolutionary design of arithmetic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Evol. Comput., 2002

Parallel Evolutionary Design of Constant-Coefficient Multipliers.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Parallel Problem Solving from Nature, 2002

Graph-based individual representation for evolutionary synthesis of arithmetic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2002 Congress on Evolutionary Computation, 2002

2001

Evolutionary graph generation system with transmigration capability for arithmetic circuit design.

[BibT_eX]

[DOI]