Naoaki Narumi

According to our database, Naoaki Narumi authored at least 4 papers between 1988 and 1991.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

1991

A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array.

Tai-ichi Otsuji, Naoaki Narumi

IEEE J. Solid State Circuits, May, 1991

1989

A 10-ps resolution, process-insensitive timing generator IC.

Tai-ichi Otsuji, Naoaki Narumi

IEEE J. Solid State Circuits, October, 1989

1988

Key Technologies for 500 MHz VLSI Test System "ULTIMATE".

Teruo Tamama, Naoaki Narumi, Tai-ichi Otsuji, Masao Suzuki, Tsuneta Sudo

Proceedings of the Proceedings International Test Conference 1988, 1988

Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE".

Yoshimitsu Sakagawa, Yusio Akazawa, Naoaki Narumi, Akira Yoshii, Tsuneta Sudo

Proceedings of the Proceedings International Test Conference 1988, 1988