Nanjian Wu
Orcid: 0000-0001-8022-0262
According to our database1,
Nanjian Wu
authored at least 121 papers
between 2006 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Ghost Reservoir: A Memory-Efficient Low-Power and Real-Time Neuromorphic Processor of Liquid State Machine With On-Chip Learning.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2024
A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision.
IEEE J. Solid State Circuits, June, 2024
A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
DT-SCNN: dual-threshold spiking convolutional neural network with fewer operations and memory access for edge applications.
Frontiers Comput. Neurosci., 2024
A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 0.144 mm<sup>2</sup>12.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 64Gb/s Si-Photonic Micro-Ring Resonator Transceiver with Co-designed CMOS Driver and TIA for WDM Optical-IO.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2024
2023
A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests.
Sci. China Inf. Sci., May, 2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 16.4kPixel 3.08-to-3.86THz Digital Real-Time CMOS Image Sensor with 73dB Dynamic Range.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 0.0035-mm<sup>2</sup> 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
MorphBungee: A 65nm 7.2mm<sup>2</sup> 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
Live Demonstration: Face Recognition at The Edge Using Fast On-Chip Deep Learning Neuromorphic Chip.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. Video Technol., 2022
A Provisional Labels-Reduced, Real-Time Connected Component Labeling Algorithm for Edge Hardware.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity.
IEEE Trans. Biomed. Circuits Syst., 2022
Sensors, 2022
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR.
IEEE J. Solid State Circuits, 2022
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
MorphBungee: An Edge Neuromorphic Chip for High-Accuracy On-Chip Learning of Multiple-Layer Spiking Neural Networks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
A 0.006-mm<sup>2</sup>6-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 0.004-mm<sup>2</sup> O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
DeepTempo: A Hardware-Friendly Direct Feedback Alignment Multi-Layer Tempotron Learning Rule for Deep Spiking Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Low-Cost High-Speed Object Tracking VLSI System Based on Unified Textural and Dynamic Compressive Features.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps.
Sensors, 2021
Sensors, 2021
CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features.
Neurocomputing, 2021
TripleBrain: An Edge Neuromorphic Architecture for High-accuracy Single-layer Spiking Neural Network with On-chip Self-organizing and Reinforcement Learning.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Pixel-Parallel Array Processor without Computational Logic for Computational Image Sensors.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021
2020
Quantizing Oriented Object Detection Network via Outlier-Aware Quantization and IoU Approximation.
IEEE Signal Process. Lett., 2020
A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification.
Sensors, 2020
A Discrete-Time Audio ΔΣ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques.
IEEE J. Solid State Circuits, 2020
A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS.
IEEE J. Solid State Circuits, 2020
TBC-Net: A real-time detector for infrared small target detection using semantic constraint.
CoRR, 2020
Deterministic conversion rule for CNNs to efficient spiking convolutional neural networks.
Sci. China Inf. Sci., 2020
A verification method for array-based vision chip using a fixed-point neural network simulation tool.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
A 28GBaud High-Swing Linear Mach-Zehnder Modulators Driver for PAM-4 and Coherent Optical Communications.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper).
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
2019
An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application.
IET Circuits Devices Syst., 2019
Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors.
IEICE Electron. Express, 2019
A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits.
Sci. China Inf. Sci., 2019
High-speed target tracking system based on multi-interconnection heterogeneous processor and multi-descriptor algorithm.
Sci. China Inf. Sci., 2019
Efficient Reservoir Encoding Method for Near-Sensor Classification with Rate-Coding Based Spiking Convolutional Neural Networks.
Proceedings of the Advances in Neural Networks - ISNN 2019, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. Video Technol., 2018
A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2017
High-Speed Target Tracking System Based on a Hierarchical Parallel Vision Processor and Gray-Level LBP Algorithm.
IEEE Trans. Syst. Man Cybern. Syst., 2017
A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter.
IEICE Electron. Express, 2017
High-speed visual target tracking with mixed rotation invariant description and skipping searching.
Sci. China Inf. Sci., 2017
Sci. China Inf. Sci., 2017
A low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end for IoT applications.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 256×256 time-of-flight image sensor based on center-tap demodulation pixel structure.
Sci. China Inf. Sci., 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor.
Sci. China Inf. Sci., 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
An efficient layered ABV methodology for vision system on chip based on heterogeneous parallel processors.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A novel vision chip architecture for image recognition based on convolutional neural network.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network.
IEEE J. Solid State Circuits, 2014
Sci. China Inf. Sci., 2014
Sci. China Inf. Sci., 2014
A massively parallel keypoint detection and description (MP-KDD) algorithm for high-speed vision chip.
Sci. China Inf. Sci., 2014
Sci. China Inf. Sci., 2014
7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
J. Circuits Syst. Comput., 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
2011
IEEE Trans. Biomed. Circuits Syst., 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
An accurate and fast behavioral model for PLL Frequency Synthesizer phase noise/spurs prediction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
An ultra low power non-volatile memory in standard CMOS process for passive RFID tags.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006