Nandu Tendolkar
According to our database1,
Nandu Tendolkar
authored at least 6 papers
between 1999 and 2006.
Collaborative distances:
Collaborative distances:
Timeline
1999
2000
2001
2002
2003
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2005
2006
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2006
Proceedings of the 2006 IEEE International Test Conference, 2006
2005
Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
2002
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2000
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999