Nanditha Rao
Orcid: 0000-0003-2369-0836
According to our database1,
Nanditha Rao
authored at least 8 papers
between 2019 and 2024.
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Bibliography
2024
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
Hybrid Multi-tile Vector Systolic Architecture for Accelerating Convolution on FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
DSEAdd: FPGA based Design Space Exploration for Approximate Adders with Variable Bit-precision.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Architectural Exploration of Heterogeneous FPGAs for Performance Enhancement of ML Benchmarks.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
The Characterization of Errors in an FPGA-Based RISC-V Processor due to Single Event Transients.
Microelectron. J., 2022
2019
Proceedings of the 15th International Wireless Communications & Mobile Computing Conference, 2019